Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-17 10:04:26 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge "fix(intel): update sip smc config addr for agilex5" into integration

Browse source
This commit is contained in:
Mark Dykes 2024-08-21 18:03:19 +02:00 • committed by TrustedFirmware Code Review
commit f538a096ca
1 changed files with 7 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
plat/intel/soc/agilex5/include/socfpga_plat_def.h
View file

@ -1,6 +1,7 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -21,7 +22,7 @@
#define PLAT_PRIMARY_CPU_A76 0x200
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_L2_RESET_REQ 0xB007C0DE
#define PLAT_L2_RESET_REQ 0xB007C0DE
/* System Counter */
/* TODO: Update back to 400MHz.
@ -31,7 +32,7 @@
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400)
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000
#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
/* QSPI Setting */
@ -101,7 +102,7 @@
/*******************************************************************************
* WDT related constants
******************************************************************************/
#define WDT_BASE (0x10D00200)
#define WDT_BASE (0x10D00200)
/*******************************************************************************
* GIC related constants
@ -116,13 +117,13 @@
/*******************************************************************************
* SDMMC related pointer function
******************************************************************************/
#define SDMMC_READ_BLOCKS sdmmc_read_blocks
#define SDMMC_WRITE_BLOCKS sdmmc_write_blocks
#define SDMMC_READ_BLOCKS sdmmc_read_blocks
#define SDMMC_WRITE_BLOCKS sdmmc_write_blocks
/*******************************************************************************
* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
* is done and HPS should trigger warm reset via RMR_EL3.
******************************************************************************/
#define L2_RESET_DONE_REG 0x10D12218
#define L2_RESET_DONE_REG 0x10D12218
#endif /* PLAT_SOCFPGA_DEF_H */