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Merge changes from topic "nxp-drivers/add-linflex-clk" into integration

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* changes:
  feat(nxp-clk): enable UART clock
  feat(nxp-clk): add PERIPH PLL enablement
This commit is contained in:
Madhukar Pappireddy 2024-08-22 15:09:16 +02:00 • committed by TrustedFirmware Code Review
commit 5eac9fea5e
7 changed files with 126 additions and 9 deletions
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1
drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
View file

@ -9,6 +9,7 @@
#define FXOSC_BASE_ADDR (0x40050000UL)
#define ARMPLL_BASE_ADDR (0x40038000UL)
#define PERIPHPLL_BASE_ADDR (0x4003C000UL)
#define ARM_DFS_BASE_ADDR (0x40054000UL)
#define CGM0_BASE_ADDR (0x40030000UL)
#define CGM1_BASE_ADDR (0x40034000UL)

5
drivers/nxp/clk/s32cc/s32cc_clk_drv.c
View file

@ -22,6 +22,7 @@
struct s32cc_clk_drv {
uintptr_t fxosc_base;
uintptr_t armpll_base;
uintptr_t periphpll_base;
uintptr_t armdfs_base;
uintptr_t cgm0_base;
uintptr_t cgm1_base;
@ -42,6 +43,7 @@ static struct s32cc_clk_drv *get_drv(void)
static struct s32cc_clk_drv driver = {
.fxosc_base = FXOSC_BASE_ADDR,
.armpll_base = ARMPLL_BASE_ADDR,
.periphpll_base = PERIPHPLL_BASE_ADDR,
.armdfs_base = ARM_DFS_BASE_ADDR,
.cgm0_base = CGM0_BASE_ADDR,
.cgm1_base = CGM1_BASE_ADDR,
@ -91,6 +93,9 @@ static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *d
case S32CC_ARM_PLL:
*base = drv->armpll_base;
break;
case S32CC_PERIPH_PLL:
*base = drv->periphpll_base;
break;
case S32CC_ARM_DFS:
*base = drv->armdfs_base;
break;

45
drivers/nxp/clk/s32cc/s32cc_clk_modules.c
View file

@ -58,6 +58,13 @@ static struct s32cc_clkmux cgm0_mux0 =
S32CC_CLK_ARM_PLL_DFS1, 0, 0, 0);
static struct s32cc_clk cgm0_mux0_clk = S32CC_MODULE_CLK(cgm0_mux0);
static struct s32cc_clkmux cgm0_mux8 =
S32CC_SHARED_CLKMUX_INIT(S32CC_CGM0, 8, 3,
S32CC_CLK_FIRC,
S32CC_CLK_PERIPH_PLL_PHI3,
S32CC_CLK_FXOSC, 0, 0);
static struct s32cc_clk cgm0_mux8_clk = S32CC_MODULE_CLK(cgm0_mux8);
/* XBAR */
static struct s32cc_clk xbar_2x_clk =
S32CC_CHILD_CLK(cgm0_mux0_clk, 48 * MHZ, 800 * MHZ);
@ -82,6 +89,14 @@ static struct s32cc_fixed_div xbar_div12 =
static struct s32cc_clk xbar_div6_clk =
S32CC_FREQ_MODULE_CLK(xbar_div12, 4 * MHZ, 66666666);
/* Linflex */
static struct s32cc_clk linflex_baud_clk =
S32CC_CHILD_CLK(cgm0_mux8_clk, 19200, 133333333);
static struct s32cc_fixed_div linflex_div =
S32CC_FIXED_DIV_INIT(linflex_baud_clk, 2);
static struct s32cc_clk linflex_clk =
S32CC_FREQ_MODULE_CLK(linflex_div, 9600, 66666666);
/* MC_CGM1 */
static struct s32cc_clkmux cgm1_mux0 =
S32CC_SHARED_CLKMUX_INIT(S32CC_CGM1, 0, 3,
@ -107,7 +122,24 @@ static struct s32cc_clk a53_core_div10_clk =
S32CC_FREQ_MODULE_CLK(a53_core_div10, S32CC_A53_MIN_FREQ / 10,
S32CC_A53_MAX_FREQ / 10);
static struct s32cc_clk *s32cc_hw_clk_list[13] = {
/* PERIPH PLL */
static struct s32cc_clkmux periph_pll_mux =
S32CC_CLKMUX_INIT(S32CC_PERIPH_PLL, 0, 2,
S32CC_CLK_FIRC,
S32CC_CLK_FXOSC, 0, 0, 0);
static struct s32cc_clk periph_pll_mux_clk =
S32CC_MODULE_CLK(periph_pll_mux);
static struct s32cc_pll periphpll =
S32CC_PLL_INIT(periph_pll_mux_clk, S32CC_PERIPH_PLL, 2);
static struct s32cc_clk periph_pll_vco_clk =
S32CC_FREQ_MODULE_CLK(periphpll, 1300 * MHZ, 2 * GHZ);
static struct s32cc_pll_out_div periph_pll_phi3_div =
S32CC_PLL_OUT_DIV_INIT(periphpll, 3);
static struct s32cc_clk periph_pll_phi3_clk =
S32CC_FREQ_MODULE_CLK(periph_pll_phi3_div, 0, 133333333);
static struct s32cc_clk *s32cc_hw_clk_list[22] = {
/* Oscillators */
[S32CC_CLK_ID(S32CC_CLK_FIRC)] = &firc_clk,
[S32CC_CLK_ID(S32CC_CLK_SIRC)] = &sirc_clk,
@ -116,6 +148,8 @@ static struct s32cc_clk *s32cc_hw_clk_list[13] = {
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_PHI0)] = &arm_pll_phi0_clk,
/* ARM DFS */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_DFS1)] = &arm_dfs1_clk,
/* PERIPH PLL */
[S32CC_CLK_ID(S32CC_CLK_PERIPH_PLL_PHI3)] = &periph_pll_phi3_clk,
};
static struct s32cc_clk_array s32cc_hw_clocks = {
@ -124,12 +158,16 @@ static struct s32cc_clk_array s32cc_hw_clocks = {
.n_clks = ARRAY_SIZE(s32cc_hw_clk_list),
};
static struct s32cc_clk *s32cc_arch_clk_list[13] = {
static struct s32cc_clk *s32cc_arch_clk_list[18] = {
/* ARM PLL */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_MUX)] = &arm_pll_mux_clk,
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_VCO)] = &arm_pll_vco_clk,
/* PERIPH PLL */
[S32CC_CLK_ID(S32CC_CLK_PERIPH_PLL_MUX)] = &periph_pll_mux_clk,
[S32CC_CLK_ID(S32CC_CLK_PERIPH_PLL_VCO)] = &periph_pll_vco_clk,
/* MC_CGM0 */
[S32CC_CLK_ID(S32CC_CLK_MC_CGM0_MUX0)] = &cgm0_mux0_clk,
[S32CC_CLK_ID(S32CC_CLK_MC_CGM0_MUX8)] = &cgm0_mux8_clk,
/* XBAR */
[S32CC_CLK_ID(S32CC_CLK_XBAR_2X)] = &xbar_2x_clk,
[S32CC_CLK_ID(S32CC_CLK_XBAR)] = &xbar_clk,
@ -143,6 +181,9 @@ static struct s32cc_clk *s32cc_arch_clk_list[13] = {
[S32CC_CLK_ID(S32CC_CLK_A53_CORE)] = &a53_core_clk,
[S32CC_CLK_ID(S32CC_CLK_A53_CORE_DIV2)] = &a53_core_div2_clk,
[S32CC_CLK_ID(S32CC_CLK_A53_CORE_DIV10)] = &a53_core_div10_clk,
/* Linflex */
[S32CC_CLK_ID(S32CC_CLK_LINFLEX)] = &linflex_clk,
[S32CC_CLK_ID(S32CC_CLK_LINFLEX_BAUD)] = &linflex_baud_clk,
};
static struct s32cc_clk_array s32cc_arch_clocks = {

72
drivers/nxp/clk/s32cc/s32cc_early_clks.c
View file

@ -4,15 +4,18 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <drivers/clk.h>
#include <platform_def.h>
#include <s32cc-clk-drv.h>
#include <s32cc-clk-ids.h>
#include <s32cc-clk-utils.h>
#define S32CC_FXOSC_FREQ (40U * MHZ)
#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
#define S32CC_A53_FREQ (1U * GHZ)
#define S32CC_XBAR_2X_FREQ (800U * MHZ)
#define S32CC_FXOSC_FREQ (40U * MHZ)
#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
#define S32CC_A53_FREQ (1U * GHZ)
#define S32CC_XBAR_2X_FREQ (800U * MHZ)
#define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ)
#define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ
static int enable_fxosc_clk(void)
{
@ -63,6 +66,38 @@ static int enable_arm_pll(void)
return ret;
}
static int enable_periph_pll(void)
{
int ret;
ret = clk_set_parent(S32CC_CLK_PERIPH_PLL_MUX, S32CC_CLK_FXOSC);
if (ret != 0) {
return ret;
}
ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_VCO, S32CC_PERIPH_PLL_VCO_FREQ, NULL);
if (ret != 0) {
return ret;
}
ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_PHI3, S32CC_PERIPH_PLL_PHI3_FREQ, NULL);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_PERIPH_PLL_VCO);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_PERIPH_PLL_PHI3);
if (ret != 0) {
return ret;
}
return ret;
}
static int enable_a53_clk(void)
{
int ret;
@ -112,6 +147,23 @@ static int enable_xbar_clk(void)
return ret;
}
static int enable_uart_clk(void)
{
int ret;
ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX8, S32CC_CLK_PERIPH_PLL_PHI3);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_LINFLEX_BAUD);
if (ret != 0) {
return ret;
}
return ret;
}
int s32cc_init_early_clks(void)
{
int ret;
@ -128,6 +180,11 @@ int s32cc_init_early_clks(void)
return ret;
}
ret = enable_periph_pll();
if (ret != 0) {
return ret;
}
ret = enable_a53_clk();
if (ret != 0) {
return ret;
@ -138,5 +195,10 @@ int s32cc_init_early_clks(void)
return ret;
}
ret = enable_uart_clk();
if (ret != 0) {
return ret;
}
return ret;
}

8
include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
View file

@ -87,4 +87,12 @@
#define S32CC_CLK_XBAR_DIV4 S32CC_ARCH_CLK(11)
#define S32CC_CLK_XBAR_DIV6 S32CC_ARCH_CLK(12)
/* Periph PLL */
#define S32CC_CLK_PERIPH_PLL_MUX S32CC_ARCH_CLK(13)
#define S32CC_CLK_PERIPH_PLL_VCO S32CC_ARCH_CLK(14)
#define S32CC_CLK_MC_CGM0_MUX8 S32CC_ARCH_CLK(15)
#define S32CC_CLK_LINFLEX_BAUD S32CC_ARCH_CLK(16)
#define S32CC_CLK_LINFLEX S32CC_ARCH_CLK(17)
#endif /* S32CC_CLK_IDS_H */

1
include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
View file

@ -30,6 +30,7 @@ enum s32cc_clk_source {
S32CC_SIRC,
S32CC_ARM_PLL,
S32CC_ARM_DFS,
S32CC_PERIPH_PLL,
S32CC_CGM0,
S32CC_CGM1,
};

3
plat/nxp/s32/s32g274ardb2/include/platform_def.h
View file

@ -54,8 +54,7 @@
/* Console settings */
#define UART_BASE UL(0x401C8000)
#define UART_BAUDRATE U(115200)
/* FIRC clock */
#define UART_CLOCK_HZ U(48000000)
#define UART_CLOCK_HZ U(125000000)
#define S32G_FIP_BASE UL(0x34100000)
#define S32G_FIP_SIZE UL(0x100000)