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feat(cpufeat): add new feature state for asymmetric features
Introduce a new feature state CHECK_ASYMMETRIC to cater for the features which are asymmetric across cores. This state is useful for platforms which has architectural asymmetric cores (A feature is only present in one type of core e.g. big). This state is similar to FEAT_STATE_CHECK (dynamic detection) except that feature state is also checked on each core during warmboot path and override the context (just for asymmetric features) which was setup by core executing CPU_ON call. Only Non-secure context will be re-checked as secure and realm context is created on same core. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ic78a0b6ca996e0d7881c43da1a6a0c422f528ef3
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3 changed files with 32 additions and 12 deletions
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@ -98,14 +98,15 @@ feature set, and thereby save and restore the configuration associated with them
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4. **Dynamic discovery of Feature enablement by EL3**
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TF-A supports three states for feature enablement at EL3, to make them available
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TF-A supports four states for feature enablement at EL3, to make them available
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for lower exception levels.
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.. code:: c
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#define FEAT_STATE_DISABLED 0
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#define FEAT_STATE_ENABLED 1
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#define FEAT_STATE_CHECK 2
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#define FEAT_STATE_DISABLED 0
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#define FEAT_STATE_ENABLED 1
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#define FEAT_STATE_CHECK 2
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#define FEAT_STATE_CHECK_ASYMMETRIC 3
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A pattern is established for feature enablement behavior.
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Each feature must support the 3 possible values with rigid semantics.
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@ -119,7 +120,26 @@ Each feature must support the 3 possible values with rigid semantics.
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- **FEAT_STATE_CHECK** - same as ``FEAT_STATE_ALWAYS`` except that the feature's
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existence will be checked at runtime. Default on dynamic platforms (example: FVP).
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.. note::
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- **FEAT_STATE_CHECK_ASYMMETRIC** - same as ``FEAT_STATE_CHECK`` except that the feature's
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existence is asymmetric across cores, which requires the feature existence is checked
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during warmboot path also. Note that only limited number of features can be asymmetric.
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.. note::
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Only limited number of features can be ``FEAT_STATE_CHECK_ASYMMETRIC`` this is due to
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the fact that Operating systems are designed for SMP systems.
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There are no clear guidelines what kind of mismatch is allowed but following pointers
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can help making a decision
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- All mandatory features must be symmetric.
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- Any feature that impacts the generation of page tables must be symmetric.
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- Any feature access which does not trap to EL3 should be symmetric.
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- Features related with profiling, debug and trace could be asymmetric
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- Migration of vCPU/tasks between CPUs should not cause an error
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Whenever there is asymmetric feature support is added for a feature TF-A need to add
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feature specific code in context management code.
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.. note::
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``FEAT_RAS`` is an exception here, as it impacts the execution of EL3 and
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it is essential to know its presence at compile time. Refer to ``ENABLE_FEAT``
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macro under :ref:`Build Options` section for more details.
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@ -498,4 +518,4 @@ Realm worlds.
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.. |Context Init WarmBoot| image:: ../resources/diagrams/context_init_warmboot.png
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.. _Trustzone for AArch64: https://developer.arm.com/documentation/102418/0101/TrustZone-in-the-processor/Switching-between-Security-states
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.. _Security States with RME: https://developer.arm.com/documentation/den0126/0100/Security-states
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.. _lib/el3_runtime/(aarch32/aarch64): https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/el3_runtime
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.. _lib/el3_runtime/(aarch32/aarch64): https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/el3_runtime
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@ -11,8 +11,9 @@
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void detect_arch_features(void);
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/* Macro Definitions */
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#define FEAT_STATE_DISABLED 0
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#define FEAT_STATE_ALWAYS 1
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#define FEAT_STATE_CHECK 2
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#define FEAT_STATE_DISABLED 0
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#define FEAT_STATE_ALWAYS 1
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#define FEAT_STATE_CHECK 2
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#define FEAT_STATE_CHECK_ASYMMETRIC 3
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#endif /* FEAT_DETECT_H */
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@ -142,7 +142,7 @@ endfunc fpregs_context_restore
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* always enable DIT in EL3
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*/
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#if ENABLE_FEAT_DIT
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#if ENABLE_FEAT_DIT == 2
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#if ENABLE_FEAT_DIT >= 2
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mrs x8, id_aa64pfr0_el1
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and x8, x8, #(ID_AA64PFR0_DIT_MASK << ID_AA64PFR0_DIT_SHIFT)
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cbz x8, 1f
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@ -166,8 +166,7 @@ endfunc fpregs_context_restore
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.macro restore_mpam3_el3
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#if ENABLE_FEAT_MPAM
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#if ENABLE_FEAT_MPAM == 2
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#if ENABLE_FEAT_MPAM >= 2
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mrs x8, id_aa64pfr0_el1
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lsr x8, x8, #(ID_AA64PFR0_MPAM_SHIFT)
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and x8, x8, #(ID_AA64PFR0_MPAM_MASK)
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