Set maximum power level to 1 as power management isn't implemented yet.
Change-Id: I26cefbb5e199944d371bf06a76b2c41f73d38585
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
STM32 MPUs use U-Boot as BL33. It can handle being booted at EL2.
Add a new STM32MP_BL33_EL1 config boolean. If defined BL33 will start
at EL1 and with INIT_UNUSED_NS_EL2 defined to Iiitialize the unused EL2
registers.
Change BL33 spsr parameter in bl2_mem_params_descs[] to use MODE_EL2
or MODE_EL1 depending on this flag. Default to MODE_EL1 as kernel
isn't able to boot at EL2 yet.
Change-Id: I6a8b35280d454d8140d7b28f0a5fc9b9a5093d6d
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
SPE and SVE for non-secure world are not supported on Arm v8.0.
Disable the corresponding flags. This also saves a bit of memory.
Change-Id: I323fb7410393ea9711759be4c47848316fb68860
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Handoff structures are populated by executable entry point
information tag based bl32/bl33 entries present in transfer list.
The upstream code is having problem with the last TL entry
particularly when the tags for two entries are same.
While tlc tool dumps all entries correctly, transfer_list_dump() in
upstream code does not provide information about the last entry in TL.
Enabling TRANSFER_LIST also enables BL1_SOURCES and BL2_SOURCES in
transfer_list.mk thereby enabling bl1/bl2 builds.
bl1/bl2 builds are disabled by turning off NEED_BL1/NEED_BL2
build flags.
Change-Id: I55ddccc1ab266cc5a609423d304a5e5c282e17f6
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Fix CCU settings for cache maintenance.
Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Update preloaded_bl33_base for legacy product for Yocto.
The Yocto Jenkins build was initially configured to build products
where the starting of the DDR is from 0x0000 0000. And if there is
no NS_image_offset set, the Jenkins is not able to acquire the correct
address offset to boot up the system. However, in the direct OS boot,
there is no issue as the user shall always include the address offset
during the compilation phase. Otherwise, the code shall execute the
default address offset. Besides that, this also provides the
flexibility to user to customize their SoC design by not restricted
to the default address.
SDMMC block size. It was changed due to the need when boot to Linux.
Kernel.itb size is big thus we have to increase the available reading
block size. Otherwise for normal U-boot and Zephyr it shall not be
reading a big block size to avoid "garbage" data.
Change-Id: I1c2a22db28bf0ada734563e40efd4f5749951273
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Enable and update code for TF-A direct boot Linux
for Agilex platform.
Change-Id: Id95986b7015a2a01f0aff80e1c7d8f8bb8fb4637
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Add the basic CPU library code to support Cortex-A720AE.
The overall library code is adapted based on Cortex-A720 code.
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Change-Id: I3d64dc5a3098cc823e656a5ad3ea05cd71598dc6
For minimal BL31 setup, GIC and tick must be initialized.
Change-Id: I8d62253e93b77cd8ce8091ccc9ea88208bdd6053
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
BL31 will need to access a device tree for several configurations (UART,
GIC, OTP mapping...).
Create a BL31 device tree (SOC_FW_CONFIG). It is loaded in DDR, in a
spare area.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I320a05859e1aa3dd8db9a274e7201075a8c250c2
This correct the MISRA violation C2012-8.13:
A pointer should point to a const-qualified type whenever possible.
Added const qualifier to pointer variables and function arguments.
Change-Id: I33cc594816809a118bff369d98d5689a96f6867f
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This correct the MISRA violation C2012-8.13:
A pointer should point to a const-qualified type whenever possible.
Added const qualifier to pointer in the function arguments.
Change-Id: If1f86a01a8bcd7f9be48b5ca3a6a00df439f2fab
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Recent change [1], caused failure in the TC2 run and this
change meant to be for TC3 and TC4.
[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/31424
Change-Id: Ibfd604a842815bcf6d413dcba2c440df81dbb486
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
It used to be the case that a FEAT_RME build could not be built with
FEAT_BRBE support. BRBE doesn't have a 3-world aware disable and
MDCR_EL3 was not context switched to allow for disabling in Realm world.
As of commit 123002f917 MDCR_EL3 is
context switched. Since the flag for BRBE support is
ENABLE_BRBE_FOR_NS, move brbe_enable() to only happen for NS world. The
other worlds will see BRBE disabled and branch recording prohibited.
This allows for a build with both RME and BRBE.
Note that EL2 BRBE registers are not context switched. Further work is
needed if non-NS support is required.
Change-Id: I82f0f08399dcd080902477dc9636bc4541685f89
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Enable support for Dynamic XLAT Tables by default for
AMD Versal Gen 2 Platform.
Change-Id: I532d9b208b0e7d8a7b1ffad741cc6c1cec0bd2ab
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Replace #if defined(TRANSFER_LIST) by #if TRANSFER_LIST.
By default TRANSFER_LIST macro is defined with value 0 in Makefile.
So checking if the macro is defined will always be true and instead
need to check the value of the macro to add the conditional code.
Change-Id: I90b06f378326d5e03ad576377ad173e81b100f56
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Implement burst speed read/write for SOC and LWSOC. Set bridge control
register to enable the register bit
Change-Id: I815b912cb90d79a548163d198eea177d70dfbc0d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Update hand-off data structure to include agilex5
platform specific parameters.
Change-Id: Ic610e2d8da7488e49462293d13293e26520579e2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Add basic CPU library code to support the Arcadia CPU.
Change-Id: Iecb0634dc6dcb34e9b5fda4902335530d237cc43
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
The FPGA_CONFIG_SIZE is actually the end address of FPGA_CONFIG_ADDR
Thus, we need to add in the DDR base address which is 0x8000 0000.
Change-Id: I177596243e0616c6eadc2fa388e85e28692dc8f7
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
The errata framework has a helper to invoke workarounds, complete with a
cpu rev_var check. We can use that directly instead of the
apply_cpu_pwr_dwn_errata to save on some code, as well as an extra
branch. It's also more readable.
Also, apply_erratum invocation in cpu files don't need to check the
rev_var as that was already done by the cpu_ops dispatcher for us to end
up in the file.
Finally, X2 erratum 2768515 only applies in the powerdown sequence, i.e.
at runtime. It doesn't achieve anything at reset, so we can label it
accordingly.
Change-Id: I02f9dd7d0619feb54c870938ea186be5e3a6ca7b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
