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fix(intel): update the size with addition 0x8000 0000 base

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The FPGA_CONFIG_SIZE is actually the end address of FPGA_CONFIG_ADDR
Thus, we need to add in the DDR base address which is 0x8000 0000.

Change-Id: I177596243e0616c6eadc2fa388e85e28692dc8f7
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang 2024-09-25 13:56:38 +08:00 • committed by Tang Sieu Mun
parent b6f2e376a8
commit 9978a3fd8b
1 changed files with 1 additions and 1 deletions
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2
plat/intel/soc/agilex5/include/socfpga_plat_def.h
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@ -33,7 +33,7 @@
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000
#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x82000000
/* QSPI Setting */
#define CAD_QSPIDATA_OFST 0x10900000