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fix(brbe): allow RME builds with BRBE
It used to be the case that a FEAT_RME build could not be built with
FEAT_BRBE support. BRBE doesn't have a 3-world aware disable and
MDCR_EL3 was not context switched to allow for disabling in Realm world.
As of commit 123002f917
MDCR_EL3 is
context switched. Since the flag for BRBE support is
ENABLE_BRBE_FOR_NS, move brbe_enable() to only happen for NS world. The
other worlds will see BRBE disabled and branch recording prohibited.
This allows for a build with both RME and BRBE.
Note that EL2 BRBE registers are not context switched. Further work is
needed if non-NS support is required.
Change-Id: I82f0f08399dcd080902477dc9636bc4541685f89
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
This commit is contained in:
parent
742d0e6ef3
commit
9890eab574
4 changed files with 10 additions and 17 deletions
8
Makefile
8
Makefile
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@ -597,19 +597,11 @@ endif #(SUPPORT_STACK_MEMTAG)
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################################################################################
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# FEAT_RME
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ifeq (${ENABLE_RME},1)
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# RME doesn't support BRBE
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ENABLE_BRBE_FOR_NS := 0
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# RME doesn't support PIE
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ifneq (${ENABLE_PIE},0)
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$(error ENABLE_RME does not support PIE)
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endif
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# RME doesn't support BRBE
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ifneq (${ENABLE_BRBE_FOR_NS},0)
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$(error ENABLE_RME does not support BRBE.)
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endif
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# RME requires AARCH64
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ifneq (${ARCH},aarch64)
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$(error ENABLE_RME requires AArch64)
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@ -623,6 +623,8 @@
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/* MDCR_EL3 definitions */
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#define MDCR_EBWE_BIT (ULL(1) << 43)
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#define MDCR_E3BREC (ULL(1) << 38)
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#define MDCR_E3BREW (ULL(1) << 37)
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#define MDCR_EnPMSN_BIT (ULL(1) << 36)
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#define MDCR_MPMX_BIT (ULL(1) << 35)
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#define MDCR_MCCD_BIT (ULL(1) << 34)
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@ -760,13 +760,6 @@ static void manage_extensions_common(cpu_context_t *ctx)
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*/
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trf_enable(ctx);
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}
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if (is_feat_brbe_supported()) {
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/*
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* Enable FEAT_BRBE for Non-Secure and prohibit for Secure state.
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*/
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brbe_enable(ctx);
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}
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#endif /* IMAGE_BL31 */
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}
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@ -792,6 +785,10 @@ static void manage_extensions_nonsecure(cpu_context_t *ctx)
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debugv8p9_extended_bp_wp_enable(ctx);
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}
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if (is_feat_brbe_supported()) {
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brbe_enable(ctx);
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}
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pmuv3_enable(ctx);
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#endif /* IMAGE_BL31 */
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}
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@ -16,11 +16,13 @@ void brbe_enable(cpu_context_t *ctx)
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/*
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* MDCR_EL3.SBRBE = 0b01
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*
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* Allows BRBE usage in non-secure world and prohibited in
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* secure world.
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*
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* MDCR_EL3.{E3BREW, E3BREC} = 0b00
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* Branch recording at EL3 is disabled
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*/
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mdcr_el3_val &= ~(MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT);
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mdcr_el3_val &= ~((MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT) | MDCR_E3BREW | MDCR_E3BREC);
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mdcr_el3_val |= (0x1UL << MDCR_SBRBE_SHIFT);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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