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feat(intel): update hand-off data to include agilex5 params
Update hand-off data structure to include agilex5 platform specific parameters. Change-Id: Ic610e2d8da7488e49462293d13293e26520579e2 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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2 changed files with 18 additions and 17 deletions
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@ -11,6 +11,7 @@
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#include "agilex5_memory_controller.h"
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#include "agilex5_system_manager.h"
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#include <platform_def.h>
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/* Platform Setting */
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@ -11,12 +11,12 @@
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#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
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#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
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#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
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#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
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#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
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#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */
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#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
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#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
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#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
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#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
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#define HANDOFF_MAGIC_PERIPHERAL 0x50455249 /* PERIPHERAL */
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#define HANDOFF_MAGIC_DDR 0x5344524d /* DDR */
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#define HANDOFF_MAGIC_DDR 0x5344524d /* DDR */
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#include <socfpga_plat_def.h>
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@ -127,6 +127,8 @@ typedef struct handoff_t {
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uint32_t clock_magic;
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uint32_t clock_length;
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uint32_t _pad_0x588_0x590[2];
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/* main group PLL */
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uint32_t main_pll_nocclk;
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uint32_t main_pll_nocdiv;
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uint32_t main_pll_pllglob;
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@ -136,6 +138,8 @@ typedef struct handoff_t {
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uint32_t main_pll_pllc2;
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uint32_t main_pll_pllc3;
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uint32_t main_pll_pllm;
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/* peripheral group PLL */
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uint32_t per_pll_emacctl;
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uint32_t per_pll_gpiodiv;
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uint32_t per_pll_pllglob;
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@ -145,29 +149,25 @@ typedef struct handoff_t {
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uint32_t per_pll_pllc2;
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uint32_t per_pll_pllc3;
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uint32_t per_pll_pllm;
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/* control group */
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uint32_t alt_emacactr;
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uint32_t alt_emacbctr;
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uint32_t alt_emacptpctr;
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uint32_t alt_gpiodbctr;
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uint32_t alt_sdmmcctr;
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uint32_t alt_s2fuser0ctr;
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uint32_t alt_s2fuser1ctr;
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uint32_t alt_psirefctr;
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/* TODO: Temp added for clk manager. */
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uint32_t qspi_clk_khz;
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uint32_t alt_usb31ctr;
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uint32_t alt_dsuctr;
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uint32_t alt_core01ctr;
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uint32_t alt_core23ctr;
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uint32_t alt_core2ctr;
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uint32_t alt_core3ctr;
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uint32_t hps_osc_clk_hz;
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uint32_t fpga_clk_hz;
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/* TODO: Temp added for clk manager. */
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uint32_t ddr_reset_type;
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/* TODO: Temp added for clk manager. */
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uint32_t hps_status_coldreset;
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/* TODO: Temp remove due to add in extra handoff data */
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//uint32_t _pad_0x604_0x610[3];
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uint32_t _pad_0x604_0x610[3];
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#endif
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/* misc configuration */
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uint32_t misc_magic;
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uint32_t misc_length;
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uint32_t _pad_0x618_0x620[2];
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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/* peripheral configuration - select */
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