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fix(intel): fix CCU for cache maintenance

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Fix CCU settings for cache maintenance.

Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
This commit is contained in:
Sieu Mun Tang 2024-10-22 00:52:09 +08:00
parent 7ac7dadb55
commit f06fdb1469
5 changed files with 19 additions and 18 deletions
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1
plat/intel/soc/agilex5/include/agilex5_cache.h
View file

@ -8,5 +8,6 @@
#define AGX5_CACHE_H
void invalidate_dcache_all(void);
void invalidate_cache_low_el(void);
#endif /* AGX5_CACHE_H */

15
plat/intel/soc/agilex5/soc/agilex5_cache.S
View file

@ -9,6 +9,21 @@
#include <plat_macros.S>
.globl invalidate_dcache_all
.globl invalidate_cache_low_el
/* --------------------------------------------------------
* Invalidate for NS EL2 and EL1
* --------------------------------------------------------
*/
func invalidate_cache_low_el
mrs x0,SCR_EL3
orr x1,x0,#SCR_NS_BIT
msr SCR_EL3, x1
isb
tlbi ALLE2
dsb sy
tlbi ALLE1
dsb sy
endfunc invalidate_cache_low_el
.pushsection .text.asm_dcache_level, "ax"
func asm_dcache_level

16
plat/intel/soc/common/aarch64/plat_helpers.S
View file

@ -21,7 +21,6 @@
.globl plat_crash_console_flush
.globl platform_mem_init
.globl plat_secondary_cpus_bl31_entry
.globl invalidate_cache_low_el
.globl plat_get_my_entrypoint
@ -216,18 +215,3 @@ func plat_secondary_cpus_bl31_entry
_exception_vectors=runtime_exceptions \
_pie_fixup_size=BL31_LIMIT - BL31_BASE
endfunc plat_secondary_cpus_bl31_entry
/* --------------------------------------------------------
* Invalidate for NS EL2 and EL1
* --------------------------------------------------------
*/
func invalidate_cache_low_el
mrs x0,SCR_EL3
orr x1,x0,#SCR_NS_BIT
msr SCR_EL3, x1
isb
tlbi ALLE2
dsb sy
tlbi ALLE1
dsb sy
endfunc invalidate_cache_low_el

2
plat/intel/soc/common/include/socfpga_private.h
View file

@ -65,6 +65,4 @@ unsigned long socfpga_get_ns_image_entrypoint(void);
void plat_secondary_cpus_bl31_entry(void);
void invalidate_cache_low_el(void);
#endif /* SOCFPGA_PRIVATE_H */

3
plat/intel/soc/common/socfpga_psci.c
View file

@ -17,6 +17,9 @@
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
#include "agilex5_cache.h"
#endif
#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
#include "socfpga_plat_def.h"