Update the compiler-rt source files to the tip of llvm-project [1]
on 9th May 2024, sha 673cfcd03b7b938b422fee07d8ca4a127d480b1f
[1] https://github.com/llvm/llvm-project
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I19f2b8ea6676d365780783f902003b0e95f0f606
Further, remove reliance of mbedtls_md_psa_alg_from_type on
the actual values of the PSA_ALG_... defines.
And work around a prior bug that would try to import a
SubjectPublicKeyInfo into a PSA key. Instead, we import the
SubjectPublicKey itself.
Change-Id: Ib345b0bd4f2994f366629ed162d18814fd05aa2b
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
This patch adds support for preserving DSU PMU registers
over a power cycle in TC platform.
These PMU registers need to be manually saved/restored
because they are part of cluster power domain and OS
doesn't know when DSU is powered OFF.
Change-Id: Ife9573f205d99d092039cb95674e7434bb5f9239
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Adds driver support to preserve DSU PMU register values over a DSU
power cycle. This driver needs to be enabled by the platforms that
support DSU and also need it's PMU registers to be preserved
Change-Id: I7fc68a3d7d99ee369379aa5cd114fffc763fc0d2
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
This patch adds an API(plat_cluster_id_by_mpidr)
that retrieves the cluster ID by looking at
the MPIDR_EL1 for platforms that have ARM_PLAT_MT set
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I0266f2e49a3114d169a7708d7ddbd4f6229a7a41
The PSA FWU support is significantly matured in terms of
its design, threat model documentation, and implementation
as well as its adherence to the latest PSA FWU specifications.
Consequently, the experimental mark for this feature has been
removed.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia6611e0c71485413b0da885f41ac59c93038e480
The DICE_PROTECTION_ENVIRONMENT support has been marked as experimental
since it has not incorporated into the threat model.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ic1ea4d59fd8a3fde7ce0404488a56e9d11bc1b85
With commit af3e8e63b switching from Boot console to runtime console is
consolidated and been moved to just before exiting bl31 and removed from
platform runtime setup hooks.
For Arm platform's runtime hook has not removed switching of console
causing runtime console to be used for Runtime instrumentation logs
which is just before bl31 exit. Causing a CI sript fail as it expects
the logs on boot console.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ia3728d17635f993911099f9d6a6938e55f45de42
Commit@f7679d437d5f27a3168f017db8d42bc561ac0c59
PMF is moved under vendor specific EL3 range, part of this
we have introduced each sub-service have an version scheme[1].
- Current PMF is not handling correctly identifying all FID's
under it so handle this correctly.
- Minor refactor to use existing macro GET_SMC_NUM rather than manual
parsing to find the SMC number.
[1]:
https://trustedfirmware-a.readthedocs.io/en/latest/components/ven-el3-service.html
Change-Id: I7a4c8936e42d4a579f0243fa3d06015540caca37
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is internal LLC.
Some systems which may have External LLC can enable the External LLC
presece with the build option 'NEOVERSE_Nx_EXTERNAL_LLC'.
Change-Id: I2567283a55c0d6e2f9fd986b7dbab91c7a815d3d
Signed-off-by: Younghyun Park <younghyunpark@google.com>
* changes:
feat(stm32mp2): use early traces
feat(st-bsec): use early traces
refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CONSOLE
feat(console): introduce EARLY_CONSOLE
feat(bl32): create an sp_min_setup function
* changes:
refactor(tc): move SCMI nodes into the 'firmware' node
refactor(tc): move MHUv2 property to tc2.dts
refactor(tc): drop the 'mhu-protocol' property in DT binding
refactor(tc): append properties in DT bindings
refactor(tc): move SCMI clock DT binding into tc-base.dtsi
refactor(tc): introduce a new file tc-fpga.dtsi
refactor(tc): move out platform specific DT binding from tc-base.dtsi
refactor(tc): move out platform specific code from tc_vers.dtsi
refactor(tc): add platform specific DT files
refactor(tc): rename 'tc_fvp.dtsi' to 'tc-fvp.dtsi'
refactor(tc): introduce a new macro ADDRESSIFY()
Refactor console_flush() and console_switch_state(CONSOLE_FLAG_RUNTIME)
to bl31_main(). This has been done per the recommendation in TF-A
mailing list. These calls need to be the last calls, after any runtime
initialization has been done, before BL31 exits.
All platforms that override the generic implementation of
bl31_plat_runtime_setup() have been refactored. The console_flush()
and console_switch_state() calls have been removed as they become
part of bl31_main() function.
Any platform that don't need to make any change to the generic (weak)
implementation of bl31_plat_runtime_setup() don't need to override it
in their platforms.
Change-Id: I6d04d6daa9353daeaa7e3df9e9adf6f322a917b8
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
TF-A plans to move the console_flush() and
console_switch_state(CONOSLE_FLAG_RUNTIME) calls to bl31_main() just
before BL31 exits.
For now we are mimicking the generic implementation by calling flush
and changing the console state to runtime at the end of
bl31_plat_runtime_setup() for each platform. This is so that each
platform can test it prior to moving flush and switch to bl31_main().
This patch affects the synquacer SoC of the socionext platform.
Change-Id: I85a251e3d9732c5fb5010c3c8bb7323c4f57fa96
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
TF-A plans to move the console_flush() and
console_switch_state(CONOSLE_FLAG_RUNTIME) calls to bl31_main() just
before BL31 exits.
For now we are mimicking the generic implementation by calling flush
and changing the console state to runtime at the end of
bl31_plat_runtime_setup() for each platform. This is so that each
platform can test it prior to moving flush and switch to bl31_main().
This patch affects the nxp platform only.
Change-Id: Ic55334a4a69b57f3c18799da12f4f521ce9de423
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
TF-A plans to move the console_flush() and
console_switch_state(CONOSLE_FLAG_RUNTIME) calls to bl31_main() just
before BL31 exits.
For now we are mimicking the generic implementation by calling flush
and changing the console state to runtime at the end of
bl31_plat_runtime_setup() for each platform. This is so that each
platform can test it prior to moving flush and switch to bl31_main().
This patch affects Nvidia platform only.
Change-Id: I78c148f50e8ee881e1816cab6eeea3765dc469e5
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
TF-A plans to move the console_flush() and
console_switch_state(CONOSLE_FLAG_RUNTIME) calls to bl31_main() just
before BL31 exits.
For now we are mimicking the generic implementation by calling flush
and changing the console state to runtime at the end of
bl31_plat_runtime_setup() for each platform. This is so that each
platform can test it prior to moving flush and switch to bl31_main().
This patch affects the Hisilicon SoCs (poplar, hikey, hikey960).
Change-Id: I0cbb0644377f663e880310362abb4308e24f0cef
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.
This patch affects Xilinx SoCs only.
Change-Id: Iea4cf920934bbde4312f40c8c7b3e0f56a316e86
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.
This patch affects the Mediatek platform only.
Change-Id: I83beee28ed856bc9b2f3131aa577be9bfa529028
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.
This patch only affects the Armada SoC of Marvell's platform.
Change-Id: I7082fdb8c5507cd1ce5915d67e61e638605982e0
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.
This patch affects the Freescale/NXP SoCs imx93, imx8qm and imx8qx.
Change-Id: Iece74579e1d15eeeb8279db0c53d74bce45545bd
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.
This patch affects the Broadcom platform only.
Change-Id: I693f749bbf56911638b03e069659e86b95b1050e
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
As per the MISRA-C standards, there should be proc == NULL not just
!proc.
Fix the same.
Change-Id: I0e7650c09b045882a0235869d7ef9fca27f96d9a
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
The upstream coverity tool has reported the null pointer dereferences
(NULL_RETURNS) warning.
The coverity warning,
Dereferencing a pointer that might be "NULL" "proc" when calling
"pm_client_suspend".
Fix the same by checking the NULL before processing further.
Change-Id: I33acead9250bab0ed24b94aa1c1bdc31e80de771
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Update parent_idx support in psci_validate_state_coordination() as
it is done in psci_do_state_coordination(). The modified loop verifies
the targeted state for all the branch up to end_pwrlvl in the topology
for the current cpu.
Fixes: 606b743007 ("feat(psci): add support for OS-initiated mode")
Change-Id: I14420f64a18b543eb4e10a1279f51cc17558c13c
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
In the ARM recommended StateID Encoding, the index for the power
level where the calling core is last to go idle use the last niblle
of the StateId.
Even if this nibble is necessary for OS-initiated mode, it can be
used by caller even when this OSI mode is not used.
In arm_validate_power_state() function, the StateId is compared with
content of arm_pm_idle_states[] build with the arm_make_pwrstate_lvl2
macro, without Last in Level information. So it is safe to mask this
nibble for ARM platform in all the cases, and that avoids issues with
caller with use the same StateId encoding with OSI mode activated or
not (in tftf tests for example, the input(power state) parameter =
(0x40001022) and the associated power state is 0x40000022).
Change-Id: I45e8e2b8f526fb61b94cf134d7d4aa3bac4c215d
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This patch adds some documentation for the context management library.
It mainly covers the design at a higher level, with more focus on
the cold boot and warm boot entries as well as the operations
involved during context switch. Further it also includes a section
on feature enablement for individual world contexts.
Change-Id: I77005730f4df7f183f56a2c6dd04f6362e813c07
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* changes:
build: improve diagnostics for unrecognized toolchain tools
build(rzg): separate BL2 and BL31 SREC generation
build(rcar): separate BL2 and BL31 SREC generation
build: separate preprocessing from DTB compilation
build: remove `MAKE_BUILD_STRINGS` function
The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is internal LLC.
Some systems which may have External LLC can enable the External LLC
presece with new build option 'NEOVERSE_Vx_EXTERNAL_LLC'.
Change-Id: I740947f1ef78e31626dc5b96f6d6dc6658d0120f
Signed-off-by: Younghyun Park <younghyunpark@google.com>
