The following system registers are made part of save and restore
operations for EL1 context:
TRFCR_EL1
SCXTNUM_EL0
SCXTNUM_EL1
GCSCR_EL1
GCSCRE0_EL1
GCSPR_EL1
GCSPR_EL0
Change-Id: I1077112bdc29a6c9cd39b9707d6cf10b95fa15e3
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Device memory region specified in an SP manifest are now validated
against the device memory defined in the SPMC manifest. Therefore
we need to add the device memory used in the tf-a-tests to the SPMC
manifests.
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: I47376e67c700705d12338d7078292618a15d5546
The patch 8754cc5 accidentally removes the declaration of
gpt_tlbi_by_pa_ll() and hence breaks RME builds. This patch
fixes the same.
signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I2523982fc48bca2a1f1a36fd9bd3803b01c6916a
Check return value from pm_get_proc() to make sure that CPU is valid.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If51b5d42ce87f31fd732ab58ae8fcd0e2db0a2a8
Since the TC1 platform has been eliminated from the TF-A source code
and CI script repository, updated the deprecation table to remove its
entry.
Change-Id: I93ae03e1f810666e9a6d0c6172a322ff1e960c71
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Cortex-X4 erratum 2740089 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before the isb in the power down sequence.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest
Change-Id: I1d0fa4dd383437044a4467591f65a4a8514cabdc
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
There's a typo in the romlib design document when referring to
the generator script. It should be romlib_generator.py instead
of romlib_generate.py so fixed this typo.
Change-Id: I6db7ee66b13c2b0b9d8511da7e0d1b058366281b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
An upcoming change to the RME support code will use atomic instructions
introduced in Armv8.1 in order to implement bitlocks. In order to do
this, the code needs to be built with appropriate -march compiler flag
(otherwise the assembler complains about invalid instructions). One way
to do this is specifying ARM_ARCH_MAJOR/MINOR version greater than 8.0,
which is what the main Makefile does when ENABLE_RME is set.
Allow the main Makefile to override the ARM_ARCH_MAJOR/MINOR variables
on the QEMU platform, so that it can also build the bitlock functions.
This only affects firmware built with ENABLE_RME, which is an
experimental feature both in TF-A and QEMU. The QEMU platform code
doesn't support booting an ENABLE_RME firmware on non-RME CPUs at the
moment.
As a result of this change, when ENABLE_RME is set,
make_helpers/arch_features.mk sets ENABLE_TRF_FOR_NS to 1, which needs
to be overridden by the QEMU Makefile.
Change-Id: I695fc98b21d07f6c84003d9e36a57cad2a3c806e
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Change the header of the license to have 2024, and
replace spaces for a tab.
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If98161ad35e1ead30e1e0d3ddb4cc6348e83d6ee
This patch modifies GPT library comments and makes
logging messages consistent with PRIx64 usage and
TF-A format used in other modules.
Minor changes are made to make the code compliant
with MISRA C requirements.
Change-Id: Ic40e1b7ac43cd9602819698d00e1ce3a8c7183ce
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
This patch removes 'gpt_' prefix from the
names of static functions for better code
readability.
Change-Id: I0398b55047a73209da598b708240fcba47c779f7
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
This patch adds tlbirpalos_XYZ() functions to support
TLBI RPALOS instructions for the 4KB-512MB invalidation
range.
Change-Id: Ife594ed6c746d356b4b1fdf97001a0fe2b5e8cd0
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
OpenSSL has brainpool support only since version 1.1.0, make sure we
put a proper guardrail around it.
Change-Id: Ia2ee686904ed80699f77b1da953546ab7538ec37
Signed-off-by: Donald Chan <donachan@tesla.com>
* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2
fix(cm): hide `cm_init_context_by_index` from BL1
fix(bl1): add missing spinlock dependency
Our code does not preclude the use of versions 1.0.x of OpenSSL.
Instead, we discourage it's use due to security concerns. Update the
documentation to reflect this.
Change-Id: I5c60907337f10b05d5c43b0384247c5d4135db50
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
auto-detecting the feature on the QEMU platforms, in order to set
SCR.ECVEN. Without this, EL2 gets undefined instruction exceptions when
trying to access the new CNTPOFF register.
Change-Id: I555a5f9a9a84fd23e64ca85219ed1599204c6bb2
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
HW_CONFIG is the hardware description consumed primarly by the Linux
kernel, and for the FVP platform, TF-A runtime firmware (BL31). Due to
both needing it, two copies of this file are made in Trusted DRAM and
SRAM. The copy in Trusted DRAM is a workaround stemming from memory
constraints in SRAM. We temporarily map the range of memory in Trusted
DRAM into BL31 to allow it to consume the configuration. In principle,
however, BL31 execution should be limited to SRAM, hence reduce the
maximum size of the HW_CONFIG to 16KB in order to accommodate it in
SRAM. This is possible since in practice, the HW_CONFIG on FVP is only
about 11KB.
Change-Id: Idb5dc0637b402562b7177a2b4e2464c4f3f67da7
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
This patch adds 'bitlock_t' type and bit_lock() and
bit_unlock() to support locking/release functionality
based on individual bit position. These functions use
atomic bit set and clear instructions which require
FEAT_LSE mandatory from Armv8.1.
Change-Id: I3eb0f29bbccefe6c0f69061aa701187a6364df0c
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Currently when RSA-PSS signing is invoked, a salt length of 32 bytes
is assumed. This works well when SHA-256 is the digest algorithm, but
the standard industry practice is that the salt length should follow
the digest length (e.g. 48/64 bytes for SHA-384/SHA-512).
Various cloud services' key management services (KMS) offering have
such restrictions in place, so if someone wants to integrate cert_create
against these services for signing key/content certs, they will have
problem with integration.
Furthermore, JWS (RFC7518) defined these specific combinations as valid
specs and other combinations are not supported:
- PS256: RSASSA-PSS using SHA-256 and MGF1 with SHA-256
- PS384: RSASSA-PSS using SHA-384 and MGF1 with SHA-384
- PS512: RSASSA-PSS using SHA-512 and MGF1 with SHA-512
Change-Id: Iafc7c60ccb36f4681053dbeb4147bac01b9d724d
Signed-off-by: Donald Chan <donachan@tesla.com>
Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.
Change-Id: I07cd4cfcacf2c991717f4c115cb0babd2c614d6f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
commit@c282384dbb45b6185b4aba14efebbad110d18e49
removed ENABLE_FEAT_MTE but missed its usage in
context structure declaration path.
All mte regs that are currently context saved/restored
are needed only when FEAT_MTE2 is enabled, so move to
usage of FEAT_MTE2 and remove FEAT_MTE usage
Change-Id: I6b4417485fa6b7f52a31045562600945e48e81b7
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Fix issue with Windows paths containing spaces. Recent toolchain
refactoring (cc277de) caused a regression in the Windows build. Ensure
toolchain path utilities wrap paths in double quoted strings.
Change-Id: I7a136e459d85cff1e9851aedf0a5272a841df09c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>
Co-authored-by: Chris Kay <chris.kay@arm.com>
These symbols are missing from BL1, which causes undefined reference
errors when linking with LTO enabled.
Change-Id: Id3eda0550c957f5ef0535f0de4ff2ad87c93b82a
Signed-off-by: Chris Kay <chris.kay@arm.com>
The core platform layer requires an implementation for the
`plat_core_pos_by_mpidr` function. This implementation is currently
missing in BL1, which causes undefined reference errors when linking
with LTO.
The FVP platform source file providing this implementation is the
`fvp_topology.c` file, so this change adds it to the BL1 sources for the
FVP.
However, the implementation of this function reaches out to the FVP
power controller driver - `fvp_pm.c` - to validate the MPIDR, and this
file has at least two other dependencies:
- `spe.c`
- `arm_gicvX.c`
Pulling these in correctly is no simple job, so I am simply removing the
power controller validation in BL1 builds.
Change-Id: I56ddf1d799f5fe7f5b0fb2b046f7fe8232b07b27
Signed-off-by: Chris Kay <chris.kay@arm.com>
The `arm_bl2_dyn_cfg_init` function is intended exclusively for BL2 - it
should not be compiled for any other bootloader image. This change hides
it for all but BL2.
Change-Id: I9fa95094dcc30f9fa4cc7bc5b3119ceae82df1ea
Signed-off-by: Chris Kay <chris.kay@arm.com>
BL1 requires the context management library but does not use or
implement `cm_init_context_by_index`. This change ensures that is not
compiled into BL1, as linking with LTO enabled causes an undefined
reference for this function.
Change-Id: I4a4602843bd75bc4f47b3e0c4c5a6efce1514ef6
Signed-off-by: Chris Kay <chris.kay@arm.com>
The spinlock functions from `spinlock.S` are used by `errata_report.c`,
which is pulled into BL1. In a normal build it appears that this
function call undergoes dead code elimination so the link error is not
reported, but when compiled with LTO enabled the linker reports an
undefined reference.
Change-Id: Id22ffa8c0c8d3ca4b4cd46f0f4aefa53907c8de5
Signed-off-by: Chris Kay <chris.kay@arm.com>
Cortex-A715 erratum 2728106 is a Cat B(rare) erratum that is present
in revision r0p0, r1p0 and r1p1. It is fixed in r1p2.
The workaround is to execute an implementation specific sequence in
the CPU.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest
Change-Id: Ic825f9942e7eb13893fdbb44a2090b897758cbc4
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Updating toolchain to the latest production release version
13.2.Rel1 publicly available on:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads
We build TF-A in CI using x86_64 Linux hosted cross toolchains:
---------------------------------------------------------------
* AArch32 bare-metal target (arm-none-eabi)
* AArch64 bare-metal target (aarch64-none-elf)
Change-Id: I9b60728bcb1a48508ccd4fcbe0114b3029509a64
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Our build system extensively uses syntax and tools that are not natively
supported by Windows shells (i.e., CMD.exe and Powershell). This
dependency necessitates a UNIX-compatible build environment. This commit
updates the prerequisites section in our documentation to reflect this.
Change-Id: Ia7e02d7a335e6c88bbaa0394650f1313cdfd6e40
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
When generating fiptool for STM32MP2, a new parameter is added to
put DDR firmware inside the FIP.
To avoid duplicating fiptool platform files, move
tools/fiptool/plat_fiptool/st/stm32mp1 files in their parent directory
and move plat_def_fip_uuid.h in in plat/st/common/include.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1dd796847869e2bfb6ee8c2bcef25c595fa5197a
