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fix(cm): add more feature registers to EL1 context mgmt

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The following system registers are made part of save and restore
operations for EL1 context:

TRFCR_EL1
SCXTNUM_EL0
SCXTNUM_EL1
GCSCR_EL1
GCSCRE0_EL1
GCSPR_EL1
GCSPR_EL0

Change-Id: I1077112bdc29a6c9cd39b9707d6cf10b95fa15e3
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
This commit is contained in:
Madhukar Pappireddy 2024-04-17 17:07:13 -05:00
parent eb69206f00
commit d6c76e6c65
4 changed files with 88 additions and 3 deletions
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12
include/arch/aarch64/arch.h
View file

@ -131,7 +131,6 @@
#define MPAMVPM6_EL2 S3_4_C10_C6_6
#define MPAMVPM7_EL2 S3_4_C10_C6_7
#define MPAMVPMV_EL2 S3_4_C10_C4_1
#define TRFCR_EL2 S3_4_C1_C2_1
#define VNCR_EL2 S3_4_C2_C2_0
#define PMSCR_EL2 S3_4_C9_C9_0
#define TFSR_EL2 S3_4_C5_C6_0
@ -1337,6 +1336,8 @@
#define GPTBR_EL3 S3_6_C2_C1_4
#define SCXTNUM_EL2 S3_4_C13_C0_7
#define SCXTNUM_EL1 S3_0_C13_C0_7
#define SCXTNUM_EL0 S3_3_C13_C0_7
/*******************************************************************************
* RAS system registers
@ -1459,9 +1460,18 @@
#define GCSCR_EL2 S3_4_C2_C5_0
#define GCSPR_EL2 S3_4_C2_C5_1
#define GCSCR_EL1 S3_0_C2_C5_0
#define GCSCRE0_EL1 S3_0_C2_C5_2
#define GCSPR_EL1 S3_0_C2_C5_1
#define GCSPR_EL0 S3_3_C2_C5_1
#define GCSCR_EXLOCK_EN_BIT (UL(1) << 6)
/*******************************************************************************
* FEAT_TRF - Trace Filter Control Registers
******************************************************************************/
#define TRFCR_EL2 S3_4_C1_C2_1
#define TRFCR_EL1 S3_0_C1_C2_1
/*******************************************************************************
* Definitions for DynamicIQ Shared Unit registers
******************************************************************************/

6
include/arch/aarch64/arch_helpers.h
View file

@ -569,6 +569,8 @@ DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el1, SCXTNUM_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el0, SCXTNUM_EL0)
/* Armv8.1 VHE Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2)
@ -606,6 +608,7 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
/* Armv8.4 FEAT_TRF Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
/* Armv8.5 MTE Registers */
@ -656,6 +659,9 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(s2por_el1, S2POR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcscre0_el1, GCSCRE0_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0)
/* DynamIQ Shared Unit power management */
DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)

29
include/lib/el3_runtime/aarch64/context.h
View file

@ -191,10 +191,35 @@
#define CTX_TCR2_REGS_END CTX_S2POE_REGS_END
#endif /* ENABLE_FEAT_TCR2 */
#if ENABLE_TRF_FOR_NS
#define CTX_TRFCR_EL1 (CTX_TCR2_REGS_END + U(0x0))
#define CTX_TRF_REGS_END (CTX_TCR2_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
#else
#define CTX_TRF_REGS_END CTX_TCR2_REGS_END
#endif /* ENABLE_TRF_FOR_NS */
#if ENABLE_FEAT_CSV2_2
#define CTX_SCXTNUM_EL0 (CTX_TRF_REGS_END + U(0x0))
#define CTX_SCXTNUM_EL1 (CTX_TRF_REGS_END + U(0x8))
#define CTX_CSV2_2_REGS_END (CTX_TRF_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
#else
#define CTX_CSV2_2_REGS_END CTX_TRF_REGS_END
#endif /* ENABLE_FEAT_CSV2_2 */
#if ENABLE_FEAT_GCS
#define CTX_GCSCR_EL1 (CTX_CSV2_2_REGS_END + U(0x0))
#define CTX_GCSCRE0_EL1 (CTX_CSV2_2_REGS_END + U(0x8))
#define CTX_GCSPR_EL1 (CTX_CSV2_2_REGS_END + U(0x10))
#define CTX_GCSPR_EL0 (CTX_CSV2_2_REGS_END + U(0x18))
#define CTX_GCS_REGS_END (CTX_CSV2_2_REGS_END + U(0x20)) /* Align to the next 16 byte boundary */
#else
#define CTX_GCS_REGS_END CTX_CSV2_2_REGS_END
#endif /* ENABLE_FEAT_GCS */
/*
* End of system registers.
* End of EL1 system registers.
*/
#define CTX_EL1_SYSREGS_END CTX_TCR2_REGS_END
#define CTX_EL1_SYSREGS_END CTX_GCS_REGS_END
/*******************************************************************************
* Constants that allow assembler code to access members of and the 'fp_regs'

44
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -1549,6 +1549,28 @@ static void el1_sysregs_context_save(el1_sysregs_t *ctx)
write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1());
}
#endif
#if ENABLE_TRF_FOR_NS
if (is_feat_trf_supported()) {
write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1());
}
#endif
#if ENABLE_FEAT_CSV2_2
if (is_feat_csv2_2_supported()) {
write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0());
write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1());
}
#endif
#if ENABLE_FEAT_GCS
if (is_feat_gcs_supported()) {
write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1());
write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1());
write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1());
write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0());
}
#endif
}
static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
@ -1636,6 +1658,28 @@ static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1));
}
#endif
#if ENABLE_TRF_FOR_NS
if (is_feat_trf_supported()) {
write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1));
}
#endif
#if ENABLE_FEAT_CSV2_2
if (is_feat_csv2_2_supported()) {
write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0));
write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1));
}
#endif
#if ENABLE_FEAT_GCS
if (is_feat_gcs_supported()) {
write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1));
write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1));
write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1));
write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0));
}
#endif
}
/*******************************************************************************