Andrew Davis aee2f33a67 feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles ... The Cortex-A72 based cores on K3 platforms can be clocked fast enough that an extra latency cycle is needed to ensure correct L2 access. Set the latency here for all A72 cores. Signed-off-by: Andrew Davis <afd@ti.com> Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883		2023-01-12 18:42:57 -06:00
..
a64fx.h	feat(cpus): add a64fx cpu to tf-a	2022-07-07 07:17:25 +09:00
aem_generic.h
cortex_a35.h	Cortex-A35: Implement workaround for errata 855472	2019-04-17 13:46:43 +01:00
cortex_a53.h	feat(cpu/cortex_a53): add L1PCTL macro definiton for CPUACTLR_EL1	2022-01-13 18:00:46 +08:00
cortex_a55.h	Cortex-A55: workarounds for errata 1221012	2019-05-28 14:19:04 +01:00
cortex_a57.h	cpus: higher performance non-cacheable load forwarding	2020-02-20 09:25:45 -08:00
cortex_a65.h	Introducing support for Cortex-A65	2019-10-02 18:12:28 +02:00
cortex_a65ae.h	Introducing support for Cortex-A65AE	2019-10-03 15:38:31 +02:00
cortex_a72.h	feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles	2023-01-12 18:42:57 -06:00
cortex_a73.h	Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__	2019-10-11 14:12:24 +02:00
cortex_a75.h	Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__	2019-08-01 13:14:12 -07:00
cortex_a76.h	fix(security): loop workaround for CVE-2022-23960 for Cortex-A76	2022-03-11 00:48:03 -06:00
cortex_a76ae.h	fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C	2022-03-21 08:57:09 -05:00
cortex_a77.h	revert(cpus): "Revert workaround for A77 erratum 1800714"	2022-10-11 09:34:05 +01:00
cortex_a78.h	fix(errata): workaround for Cortex A78 AE erratum 2395408	2022-03-24 10:55:48 +00:00
cortex_a78_ae.h	fix(errata): workaround for Cortex A78 AE erratum 2395408	2022-03-24 10:55:48 +00:00
cortex_a78c.h	fix(cpus): workaround for Cortex-A78C erratum 2376749	2022-09-08 13:25:42 +02:00
cortex_a510.h	fix(cpus): workaround for Cortex-A510 erratum 2666669	2022-10-13 16:19:50 -05:00
cortex_a710.h	fix(cpus): workaround for Cortex-A710 erratum 2291219	2022-10-27 13:46:52 +01:00
cortex_hayes.h	feat(cpu): add support for Hayes CPU	2021-09-30 19:30:39 +02:00
cortex_hunter.h	fix(security): workaround for CVE-2022-23960	2022-05-11 19:05:48 +02:00
cortex_hunter_elp_arm.h	feat(cpu): add library support for Hunter ELP	2022-10-07 12:44:04 +01:00
cortex_makalu.h	fix(security): workaround for CVE-2022-23960	2022-05-11 19:05:48 +02:00
cortex_x1.h	fix(security): workaround for CVE-2022-23960 for Cortex-X1	2022-05-11 15:24:37 +02:00
cortex_x2.h	fix(errata): workaround for Cortex-X2 erratum 2371105	2022-07-21 14:26:59 -05:00
cortex_x3.h	fix(cpus): workaround for Cortex-X3 erratum 2615812	2022-11-17 09:41:40 +00:00
cpu_macros.S	fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57	2022-03-18 01:01:34 +02:00
cpuamu.h	Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__	2019-08-01 13:14:12 -07:00
denver.h	lib: cpus: denver: add MIDR PN9 variant	2020-08-31 10:43:44 -07:00
dsu_def.h	fix(errata): workaround for DSU-110 erratum 2313941	2022-05-11 19:05:36 +02:00
generic.h	arm_fpga: Add support for unknown MPIDs	2020-09-25 15:45:50 +01:00
neoverse_e1.h	Fix wrong MIDR_EL1 value for Neoverse E1	2019-03-15 15:40:27 +00:00
neoverse_n1.h	fix(security): workaround for CVE-2022-23960	2022-03-10 23:57:14 -06:00
neoverse_n2.h	fix(cpus): workaround for Neoverse-N2 erratum 2326639	2022-10-27 13:46:52 +01:00
neoverse_n_common.h	Add support for Neoverse-N2 CPUs.	2020-11-30 19:12:56 +00:00
neoverse_poseidon.h	fix(security): workaround for CVE-2022-23960	2022-05-11 19:05:48 +02:00
neoverse_v1.h	fix(errata): workaround for Neoverse-V1 erratum 1618635	2022-08-05 15:56:30 -04:00
neoverse_v2.h	refactor(cpu): use the updated IP name for Demeter CPU	2022-10-03 15:31:40 +05:30
qemu_max.h	Add support for QEMU "max" CPU	2021-04-13 12:31:40 +01:00
rainier.h	lib/cpus: update MIDR value for rainier cpu	2020-10-09 10:43:13 +00:00