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fix(errata): workaround for Cortex-X2 erratum 2371105
Cortex-X2 erratum 2371105 is a cat B erratum that applies to revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests into older prefetches with L2 miss requests outstanding. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775100/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ib4f0caac36e1ecf049871acdea45526b394b7bad
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@ -541,6 +541,10 @@ For Cortex-X2, the following errata build flags are defined :
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Cortex-X2 CPU. This needs to be enabled only for revision r2p0 of the CPU,
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it is fixed in r2p1.
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- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to
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Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
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of the CPU and is fixed in r2p1.
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For Cortex-A510, the following errata build flags are defined :
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- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
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@ -39,6 +39,12 @@
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#define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
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/*******************************************************************************
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* CPU Auxiliary Control Register 2 definitions
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******************************************************************************/
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#define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
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/*******************************************************************************
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* CPU Auxiliary Control Register 5 definitions
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******************************************************************************/
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@ -267,6 +267,34 @@ func check_errata_2147715
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b cpu_rev_var_range
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endfunc check_errata_2147715
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/* -------------------------------------------------------
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* Errata Workaround for Cortex-X2 Erratum 2371105.
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* This applies to revisions <= r2p0 and is fixed in r2p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* -------------------------------------------------------
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*/
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func errata_x2_2371105_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2371105
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cbz x0, 1f
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/* Set bit 40 in CPUACTLR2_EL1 */
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mrs x1, CORTEX_X2_CPUACTLR2_EL1
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orr x1, x1, #CORTEX_X2_CPUACTLR2_EL1_BIT_40
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msr CORTEX_X2_CPUACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_x2_2371105_wa
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func check_errata_2371105
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/* Applies to <= r2p0. */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2371105
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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@ -304,6 +332,7 @@ func cortex_x2_errata_report
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report_errata ERRATA_X2_2083908, cortex_x2, 2083908
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report_errata ERRATA_X2_2147715, cortex_x2, 2147715
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report_errata ERRATA_X2_2216384, cortex_x2, 2216384
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report_errata ERRATA_X2_2371105, cortex_x2, 2371105
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report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960
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report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941
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@ -361,6 +390,11 @@ func cortex_x2_reset_func
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bl errata_x2_2147715_wa
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#endif
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#if ERRATA_X2_2371105
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mov x0, x18
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bl errata_x2_2371105_wa
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-X2 generic vectors are overridden to apply errata
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@ -599,6 +599,10 @@ ERRATA_X2_2216384 ?=0
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# only to revision r2p0 of the Cortex-X2 cpu, it is fixed in r2p1.
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ERRATA_X2_2147715 ?=0
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# Flag to apply erratum 2371105 workaround during reset. This erratum applies
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# to revision r0p0, r1p0 and r2p0 of the Cortex-X2 cpu and is fixed in r2p1.
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ERRATA_X2_2371105 ?=0
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# Flag to apply erratum 1922240 workaround during reset. This erratum applies
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# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
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ERRATA_A510_1922240 ?=0
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@ -1155,6 +1159,10 @@ $(eval $(call add_define,ERRATA_X2_2216384))
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$(eval $(call assert_boolean,ERRATA_X2_2147715))
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$(eval $(call add_define,ERRATA_X2_2147715))
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# Process ERRATA_X2_2371105 flag
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$(eval $(call assert_boolean,ERRATA_X2_2371105))
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$(eval $(call add_define,ERRATA_X2_2371105))
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# Process ERRATA_A510_1922240 flag
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$(eval $(call assert_boolean,ERRATA_A510_1922240))
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$(eval $(call add_define,ERRATA_A510_1922240))
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