From bc0f84de40d4f1efddfb50071fff09d32f0ea9b2 Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Tue, 12 Jul 2022 17:13:01 -0500 Subject: [PATCH] fix(errata): workaround for Cortex-X2 erratum 2371105 Cortex-X2 erratum 2371105 is a cat B erratum that applies to revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests into older prefetches with L2 miss requests outstanding. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775100/latest Signed-off-by: Bipin Ravi Change-Id: Ib4f0caac36e1ecf049871acdea45526b394b7bad --- docs/design/cpu-specific-build-macros.rst | 4 +++ include/lib/cpus/aarch64/cortex_x2.h | 6 ++++ lib/cpus/aarch64/cortex_x2.S | 34 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 52 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index de3b9bcd3..aafd00679 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -541,6 +541,10 @@ For Cortex-X2, the following errata build flags are defined : Cortex-X2 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed in r2p1. +- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to + Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 + of the CPU and is fixed in r2p1. + For Cortex-A510, the following errata build flags are defined : - ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h index 92140b1e2..863b8c8d3 100644 --- a/include/lib/cpus/aarch64/cortex_x2.h +++ b/include/lib/cpus/aarch64/cortex_x2.h @@ -39,6 +39,12 @@ #define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0 #define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) +/******************************************************************************* + * CPU Auxiliary Control Register 2 definitions + ******************************************************************************/ +#define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) + /******************************************************************************* * CPU Auxiliary Control Register 5 definitions ******************************************************************************/ diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index 3e0810ba0..c810be6b0 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S @@ -267,6 +267,34 @@ func check_errata_2147715 b cpu_rev_var_range endfunc check_errata_2147715 +/* ------------------------------------------------------- + * Errata Workaround for Cortex-X2 Erratum 2371105. + * This applies to revisions <= r2p0 and is fixed in r2p1. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * ------------------------------------------------------- + */ +func errata_x2_2371105_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2371105 + cbz x0, 1f + + /* Set bit 40 in CPUACTLR2_EL1 */ + mrs x1, CORTEX_X2_CPUACTLR2_EL1 + orr x1, x1, #CORTEX_X2_CPUACTLR2_EL1_BIT_40 + msr CORTEX_X2_CPUACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_x2_2371105_wa + +func check_errata_2371105 + /* Applies to <= r2p0. */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_2371105 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- @@ -304,6 +332,7 @@ func cortex_x2_errata_report report_errata ERRATA_X2_2083908, cortex_x2, 2083908 report_errata ERRATA_X2_2147715, cortex_x2, 2147715 report_errata ERRATA_X2_2216384, cortex_x2, 2216384 + report_errata ERRATA_X2_2371105, cortex_x2, 2371105 report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960 report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941 @@ -361,6 +390,11 @@ func cortex_x2_reset_func bl errata_x2_2147715_wa #endif +#if ERRATA_X2_2371105 + mov x0, x18 + bl errata_x2_2371105_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* * The Cortex-X2 generic vectors are overridden to apply errata diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 5be0a55d6..777c9a6a7 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -599,6 +599,10 @@ ERRATA_X2_2216384 ?=0 # only to revision r2p0 of the Cortex-X2 cpu, it is fixed in r2p1. ERRATA_X2_2147715 ?=0 +# Flag to apply erratum 2371105 workaround during reset. This erratum applies +# to revision r0p0, r1p0 and r2p0 of the Cortex-X2 cpu and is fixed in r2p1. +ERRATA_X2_2371105 ?=0 + # Flag to apply erratum 1922240 workaround during reset. This erratum applies # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1. ERRATA_A510_1922240 ?=0 @@ -1155,6 +1159,10 @@ $(eval $(call add_define,ERRATA_X2_2216384)) $(eval $(call assert_boolean,ERRATA_X2_2147715)) $(eval $(call add_define,ERRATA_X2_2147715)) +# Process ERRATA_X2_2371105 flag +$(eval $(call assert_boolean,ERRATA_X2_2371105)) +$(eval $(call add_define,ERRATA_X2_2371105)) + # Process ERRATA_A510_1922240 flag $(eval $(call assert_boolean,ERRATA_A510_1922240)) $(eval $(call add_define,ERRATA_A510_1922240))