Andrew Davis aee2f33a67 feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles ... The Cortex-A72 based cores on K3 platforms can be clocked fast enough that an extra latency cycle is needed to ensure correct L2 access. Set the latency here for all A72 cores. Signed-off-by: Andrew Davis <afd@ti.com> Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883		2023-01-12 18:42:57 -06:00
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aarch32	feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles	2023-01-12 18:42:57 -06:00
aarch64	feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles	2023-01-12 18:42:57 -06:00
errata_report.h	Workaround for Cortex A78 erratum 1951500	2021-01-13 13:54:18 -06:00
wa_cve_2017_5715.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2018_3639.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2022_23960.h	fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57	2022-03-18 01:01:34 +02:00