Andrew Davis aee2f33a67 feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles ... The Cortex-A72 based cores on K3 platforms can be clocked fast enough that an extra latency cycle is needed to ensure correct L2 access. Set the latency here for all A72 cores. Signed-off-by: Andrew Davis <afd@ti.com> Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883		2023-01-12 18:42:57 -06:00
..
aem_generic.h	cpus: Add casts to all definitions in CPU headers	2019-02-11 13:34:57 +00:00
cortex_a5.h	cpus: Add casts to all definitions in CPU headers	2019-02-11 13:34:57 +00:00
cortex_a7.h	cpus: Add casts to all definitions in CPU headers	2019-02-11 13:34:57 +00:00
cortex_a9.h	Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__	2019-08-01 13:14:12 -07:00
cortex_a12.h	cpus: Fix Cortex-A12 MIDR mask	2019-04-08 12:47:48 +02:00
cortex_a15.h	Cortex-A15: Implement workaround for errata 827671	2019-03-13 14:05:47 +00:00
cortex_a17.h	Cortex-A17: Implement workaround for errata 852421	2019-03-13 15:40:45 +00:00
cortex_a32.h	cpus: Add casts to all definitions in CPU headers	2019-02-11 13:34:57 +00:00
cortex_a53.h	cpus: Add casts to all definitions in CPU headers	2019-02-11 13:34:57 +00:00
cortex_a57.h	Cortex-A57: Implement workaround for erratum 814670	2019-02-28 09:56:58 +00:00
cortex_a72.h	feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles	2023-01-12 18:42:57 -06:00
cpu_macros.S	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00