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fix(cpus): workaround for Cortex-A78C erratum 2376749
Cortex-A78C erratum 2376749 is a Cat B erratum that applies to revisions r0p1 and r0p2 of the A78C and is currently open. The workaround is to set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches. SDEN can be found here: https://developer.arm.com/documentation/SDEN2004089/latest Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com> Change-Id: I3b29f4b7f167bf499d5d11ffef91a94861bd1383
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@ -335,6 +335,10 @@ For Cortex-A78C, the following errata build flags are defined :
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Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
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it is still open.
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- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to
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Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
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erratum is still open.
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- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to
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Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
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erratum is still open.
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@ -17,6 +17,7 @@
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* CPU Auxiliary Control register 2 specific definitions.
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* ****************************************************************************/
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#define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
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#define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
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/*******************************************************************************
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@ -17,6 +17,35 @@
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#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78C Erratum 2376749.
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* This applies to revision r0p1 and r0p2 of the A78C
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* and is currently open. It is a Cat B erratum.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x4, x17
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* --------------------------------------------------
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*/
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func errata_a78c_2376749_wa
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/* Check revision */
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mov x17, x30
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bl check_errata_2376749
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cbz x0, 1f
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/* Set CPUACTLR2_EL1[0] to 1. */
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mrs x1, CORTEX_A78C_CPUACTLR2_EL1
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orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0
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msr CORTEX_A78C_CPUACTLR2_EL1, x1
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1:
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ret x17
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endfunc errata_a78c_2376749_wa
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func check_errata_2376749
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/* Applies to r0p1 and r0p2*/
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mov x1, #0x01
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mov x2, #0x02
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b cpu_rev_var_range
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endfunc check_errata_2376749
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78C Erratum 2395411.
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* This applies to revision r0p1 and r0p2 of the A78C
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@ -151,6 +180,11 @@ func cortex_a78c_reset_func
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bl errata_a78c_2242638_wa
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#endif
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#if ERRATA_A78C_2376749
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mov x0, x18
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bl errata_a78c_2376749_wa
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#endif
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#if ERRATA_A78C_2395411
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mov x0, x18
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bl errata_a78c_2395411_wa
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@ -201,6 +235,7 @@ func cortex_a78c_errata_report
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*/
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report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
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report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
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report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
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report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
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report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
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@ -369,6 +369,10 @@ ERRATA_A78C_2132064 ?=0
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# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
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ERRATA_A78C_2242638 ?=0
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# Flag to apply erratum 2376749 workaround during reset. This erratum applies
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# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
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ERRATA_A78C_2376749 ?=0
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# Flag to apply erratum 2395411 workaround during reset. This erratum applies
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# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
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ERRATA_A78C_2395411 ?=0
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@ -964,6 +968,10 @@ $(eval $(call add_define,ERRATA_A78C_2132064))
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$(eval $(call assert_boolean,ERRATA_A78C_2242638))
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$(eval $(call add_define,ERRATA_A78C_2242638))
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# Process ERRATA_A78C_2376749 flag
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$(eval $(call assert_boolean,ERRATA_A78C_2376749))
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$(eval $(call add_define,ERRATA_A78C_2376749))
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# Process ERRATA_A78C_2395411 flag
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$(eval $(call assert_boolean,ERRATA_A78C_2395411))
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$(eval $(call add_define,ERRATA_A78C_2395411))
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