fix(cpus): workaround for Cortex-A78C erratum 2376749

Cortex-A78C erratum 2376749 is a Cat B erratum that applies
to revisions r0p1 and r0p2 of the A78C and is currently open.
The workaround is to set CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause
invalidations to other PE caches.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I3b29f4b7f167bf499d5d11ffef91a94861bd1383
This commit is contained in:
Akram Ahmad 2022-09-06 11:23:25 +01:00
parent f1f2384b3b
commit 5d3c1f5890
4 changed files with 48 additions and 0 deletions

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@ -335,6 +335,10 @@ For Cortex-A78C, the following errata build flags are defined :
Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
it is still open.
- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
erratum is still open.
- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
erratum is still open.

View file

@ -17,6 +17,7 @@
* CPU Auxiliary Control register 2 specific definitions.
* ****************************************************************************/
#define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
#define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
/*******************************************************************************

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@ -17,6 +17,35 @@
#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* --------------------------------------------------
* Errata Workaround for Cortex A78C Erratum 2376749.
* This applies to revision r0p1 and r0p2 of the A78C
* and is currently open. It is a Cat B erratum.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x4, x17
* --------------------------------------------------
*/
func errata_a78c_2376749_wa
/* Check revision */
mov x17, x30
bl check_errata_2376749
cbz x0, 1f
/* Set CPUACTLR2_EL1[0] to 1. */
mrs x1, CORTEX_A78C_CPUACTLR2_EL1
orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0
msr CORTEX_A78C_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_a78c_2376749_wa
func check_errata_2376749
/* Applies to r0p1 and r0p2*/
mov x1, #0x01
mov x2, #0x02
b cpu_rev_var_range
endfunc check_errata_2376749
/* --------------------------------------------------
* Errata Workaround for Cortex A78C Erratum 2395411.
* This applies to revision r0p1 and r0p2 of the A78C
@ -151,6 +180,11 @@ func cortex_a78c_reset_func
bl errata_a78c_2242638_wa
#endif
#if ERRATA_A78C_2376749
mov x0, x18
bl errata_a78c_2376749_wa
#endif
#if ERRATA_A78C_2395411
mov x0, x18
bl errata_a78c_2395411_wa
@ -201,6 +235,7 @@ func cortex_a78c_errata_report
*/
report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960

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@ -369,6 +369,10 @@ ERRATA_A78C_2132064 ?=0
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
ERRATA_A78C_2242638 ?=0
# Flag to apply erratum 2376749 workaround during reset. This erratum applies
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
ERRATA_A78C_2376749 ?=0
# Flag to apply erratum 2395411 workaround during reset. This erratum applies
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
ERRATA_A78C_2395411 ?=0
@ -964,6 +968,10 @@ $(eval $(call add_define,ERRATA_A78C_2132064))
$(eval $(call assert_boolean,ERRATA_A78C_2242638))
$(eval $(call add_define,ERRATA_A78C_2242638))
# Process ERRATA_A78C_2376749 flag
$(eval $(call assert_boolean,ERRATA_A78C_2376749))
$(eval $(call add_define,ERRATA_A78C_2376749))
# Process ERRATA_A78C_2395411 flag
$(eval $(call assert_boolean,ERRATA_A78C_2395411))
$(eval $(call add_define,ERRATA_A78C_2395411))