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Add support for QEMU "max" CPU

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Enable basic support for QEMU "max" CPU.
The "max" CPU does not attampt to emulate any specific CPU, but rather
just enables all the functions emulated by QEMU.

Change-Id: I69c212932ef61433509662d0fefbabb1e9e71cf2
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
This commit is contained in:
Leif Lindholm 2021-03-10 13:23:24 +00:00
parent 103ee1b1c3
commit 5d764e05e4
2 changed files with 103 additions and 0 deletions
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22
include/lib/cpus/aarch64/qemu_max.h Normal file
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/*
* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef QEMU_MAX_H
#define QEMU_MAX_H
#include <lib/utils_def.h>
/*
* QEMU MAX midr for revision 0
* 00 - Reserved for software use
* 0 - Variant
* F - Architectural features identified in ID_* registers
* 051 - 'Q', in a 12-bit field.
* 0 - Revision
*/
#define QEMU_MAX_MIDR U(0x000F0510)
#endif /* QEMU_MAX_H */

81
lib/cpus/aarch64/qemu_max.S Normal file
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/*
* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <cpu_macros.S>
#include <qemu_max.h>
func qemu_max_core_pwr_dwn
/* ---------------------------------------------
* Disable the Data Cache.
* ---------------------------------------------
*/
mrs x1, sctlr_el3
bic x1, x1, #SCTLR_C_BIT
msr sctlr_el3, x1
isb
/* ---------------------------------------------
* Flush L1 cache to L2.
* ---------------------------------------------
*/
mov x18, lr
mov x0, #DCCISW
bl dcsw_op_level1
mov lr, x18
ret
endfunc qemu_max_core_pwr_dwn
func qemu_max_cluster_pwr_dwn
/* ---------------------------------------------
* Disable the Data Cache.
* ---------------------------------------------
*/
mrs x1, sctlr_el3
bic x1, x1, #SCTLR_C_BIT
msr sctlr_el3, x1
isb
/* ---------------------------------------------
* Flush all caches to PoC.
* ---------------------------------------------
*/
mov x0, #DCCISW
b dcsw_op_all
endfunc qemu_max_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for QEMU "max". Must follow AAPCS.
*/
func qemu_max_errata_report
ret
endfunc qemu_max_errata_report
#endif
/* ---------------------------------------------
* This function provides cpu specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
* x8 - x15 having values of registers to be
* reported.
* ---------------------------------------------
*/
.section .rodata.qemu_max_regs, "aS"
qemu_max_regs: /* The ascii list of register names to be reported */
.asciz "" /* no registers to report */
func qemu_max_cpu_reg_dump
adr x6, qemu_max_regs
ret
endfunc qemu_max_cpu_reg_dump
/* cpu_ops for QEMU MAX */
declare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \
qemu_max_core_pwr_dwn, \
qemu_max_cluster_pwr_dwn