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fix(errata): workaround for Neoverse-V1 erratum 1618635

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Neoverse-V1 erratum 1618635 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
The workaround is done through the instruction patching
mechanism, which is performed by a write sequence of
IMPLEMENTATION DEFINED registers.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest/

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I53e406735cd3a2a930fdc72ebce3bbed97100168
This commit is contained in:
Juan Pablo Conde 2022-02-28 14:14:44 -05:00
parent 17e76b5eb7
commit 14a6fed5ac
4 changed files with 98 additions and 0 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -390,6 +390,10 @@ For Neoverse N1, the following errata build flags are defined :
For Neoverse V1, the following errata build flags are defined :
- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
r1p0.
- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1
CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
in r1p1.

4
include/lib/cpus/aarch64/neoverse_v1.h
View file

@ -16,6 +16,10 @@
* CPU Extended Control register specific definitions.
******************************************************************************/
#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
#define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0
#define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2
#define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3
#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)

82
lib/cpus/aarch64/neoverse_v1.S
View file

@ -26,6 +26,82 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1
#endif /* WORKAROUND_CVE_2022_23960 */
/* --------------------------------------------------
* Errata Workaround for Neoverse V1 Errata #1618635.
* This applies to revision r0p0 and is fixed in
* r1p0.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x17
* --------------------------------------------------
*/
func errata_neoverse_v1_1618635_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_1618635
cbz x0, 1f
/* Inserts a DMB SY before and after MRS PAR_EL1 */
ldr x0, =0x0
msr NEOVERSE_V1_CPUPSELR_EL3, x0
ldr x0, = 0xEE070F14
msr NEOVERSE_V1_CPUPOR_EL3, x0
ldr x0, = 0xFFFF0FFF
msr NEOVERSE_V1_CPUPMR_EL3, x0
ldr x0, =0x4005027FF
msr NEOVERSE_V1_CPUPCR_EL3, x0
/* Inserts a DMB SY before STREX imm offset */
ldr x0, =0x1
msr NEOVERSE_V1_CPUPSELR_EL3, x0
ldr x0, =0x00e8400000
msr NEOVERSE_V1_CPUPOR_EL3, x0
ldr x0, =0x00fff00000
msr NEOVERSE_V1_CPUPMR_EL3, x0
ldr x0, = 0x4001027FF
msr NEOVERSE_V1_CPUPCR_EL3, x0
/* Inserts a DMB SY before STREX[BHD}/STLEX* */
ldr x0, =0x2
msr NEOVERSE_V1_CPUPSELR_EL3, x0
ldr x0, =0x00e8c00040
msr NEOVERSE_V1_CPUPOR_EL3, x0
ldr x0, =0x00fff00040
msr NEOVERSE_V1_CPUPMR_EL3, x0
ldr x0, = 0x4001027FF
msr NEOVERSE_V1_CPUPCR_EL3, x0
/* Inserts a DMB SY after STREX imm offset */
ldr x0, =0x3
msr NEOVERSE_V1_CPUPSELR_EL3, x0
ldr x0, =0x00e8400000
msr NEOVERSE_V1_CPUPOR_EL3, x0
ldr x0, =0x00fff00000
msr NEOVERSE_V1_CPUPMR_EL3, x0
ldr x0, = 0x4004027FF
msr NEOVERSE_V1_CPUPCR_EL3, x0
/* Inserts a DMB SY after STREX[BHD}/STLEX* */
ldr x0, =0x4
msr NEOVERSE_V1_CPUPSELR_EL3, x0
ldr x0, =0x00e8c00040
msr NEOVERSE_V1_CPUPOR_EL3, x0
ldr x0, =0x00fff00040
msr NEOVERSE_V1_CPUPMR_EL3, x0
ldr x0, = 0x4004027FF
msr NEOVERSE_V1_CPUPCR_EL3, x0
/* Synchronize to enable patches */
isb
1:
ret x17
endfunc errata_neoverse_v1_1618635_wa
func check_errata_1618635
/* Applies to revision r0p0. */
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_1618635
/* --------------------------------------------------
* Errata Workaround for Neoverse V1 Errata #1774420.
* This applies to revisions r0p0 and r1p0, fixed in r1p1.
@ -425,6 +501,7 @@ func neoverse_v1_errata_report
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_V1_1618635, neoverse_v1, 1618635
report_errata ERRATA_V1_1774420, neoverse_v1, 1774420
report_errata ERRATA_V1_1791573, neoverse_v1, 1791573
report_errata ERRATA_V1_1852267, neoverse_v1, 1852267
@ -450,6 +527,11 @@ func neoverse_v1_reset_func
msr SSBS, xzr
isb
#if ERRATA_V1_1618635
mov x0, x18
bl errata_neoverse_v1_1618635_wa
#endif
#if ERRATA_V1_1774420
mov x0, x18
bl errata_neoverse_v1_1774420_wa

8
lib/cpus/cpu-ops.mk
View file

@ -442,6 +442,10 @@ ERRATA_N1_1946160 ?=0
# to revisions r0p0 of the Neoverse-N2 cpu, it is still open.
ERRATA_N2_2002655 ?=0
# Flag to apply erratum 1618635 workaround during reset. This erratum applies
# to revision r0p0 of the Neoverse V1 cpu and was fixed in the revision r1p0.
ERRATA_V1_1618635 ?=0
# Flag to apply erratum 1774420 workaround during reset. This erratum applies
# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1.
ERRATA_V1_1774420 ?=0
@ -1011,6 +1015,10 @@ $(eval $(call add_define,ERRATA_N1_1946160))
$(eval $(call assert_boolean,ERRATA_N2_2002655))
$(eval $(call add_define,ERRATA_N2_2002655))
# Process ERRATA_V1_1618635 flag
$(eval $(call assert_boolean,ERRATA_V1_1618635))
$(eval $(call add_define,ERRATA_V1_1618635))
# Process ERRATA_V1_1774420 flag
$(eval $(call assert_boolean,ERRATA_V1_1774420))
$(eval $(call add_define,ERRATA_V1_1774420))