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Merge "feat(plat/qti): fix to support cpu errata" into integration

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This commit is contained in:
Bipin Ravi 2022-08-02 21:25:24 +02:00 • committed by TrustedFirmware Code Review
commit 17e76b5eb7
14 changed files with 82 additions and 85 deletions
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2
lib/cpus/aarch64/cortex_a55.S
View file

@ -16,6 +16,8 @@
#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
.globl cortex_a55_reset_func
.globl cortex_a55_core_pwr_dwn
/* --------------------------------------------------
* Errata Workaround for Cortex A55 Errata #768277.
* This applies only to revision r0p0 of Cortex A55.

3
lib/cpus/aarch64/cortex_a76.S
View file

@ -17,6 +17,9 @@
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A76 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
.globl cortex_a76_reset_func
.globl cortex_a76_core_pwr_dwn
.globl cortex_a76_disable_wa_cve_2018_3639
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1

3
lib/cpus/aarch64/cortex_a78.S
View file

@ -17,6 +17,9 @@
#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
.globl cortex_a78_reset_func
.globl cortex_a78_core_pwr_dwn
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78
#endif /* WORKAROUND_CVE_2022_23960 */

7
plat/qti/common/inc/qti_plat.h
View file

@ -25,13 +25,14 @@ int qti_mmap_remove_dynamic_region(uintptr_t base_va, size_t size);
/*
* Utility functions common to ARM standard platforms
*/
void qti_setup_page_tables(uintptr_t total_base,
void qti_setup_page_tables(
uintptr_t total_base,
size_t total_size,
uintptr_t code_start,
uintptr_t code_limit,
uintptr_t rodata_start,
uintptr_t rodata_limit,
uintptr_t coh_start, uintptr_t coh_limit);
uintptr_t rodata_limit
);
/*
* Mandatory functions required in ARM standard platforms

7
plat/qti/common/src/aarch64/qti_helpers.S
View file

@ -72,17 +72,10 @@ func plat_reset_handler
/* save the lr */
mov x18, x30
/* Serialize CPUSS boot setup. Multi core enter simultaneously. */
ldr x0, =g_qti_cpuss_boot_lock
bl spin_lock
/* pass cold boot status. */
ldr w0, g_qti_bl31_cold_booted
/* Execuete CPUSS boot set up on every core. */
bl qtiseclib_cpuss_reset_asm
ldr x0, =g_qti_cpuss_boot_lock
bl spin_unlock
ret x18
endfunc plat_reset_handler

18
plat/qti/common/src/aarch64/qti_kryo4_gold.S
View file

@ -28,19 +28,11 @@ func qti_kryo4_gold_reset_func
mov x19, x30
bl qtiseclib_kryo4_gold_reset_asm
ret x19
mov x30, x19
b cortex_a76_reset_func
endfunc qti_kryo4_gold_reset_func
/* ----------------------------------------------------
* The CPU Ops core power down function for Kryo-3 Gold
* ----------------------------------------------------
*/
func qti_kryo4_gold_core_pwr_dwn
ret
endfunc qti_kryo4_gold_core_pwr_dwn
/* -------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Gold
* -------------------------------------------------------
@ -77,7 +69,9 @@ func qti_kryo4_gold_cpu_reg_dump
ret
endfunc qti_kryo4_gold_cpu_reg_dump
declare_cpu_ops qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \
declare_cpu_ops_wa qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \
qti_kryo4_gold_reset_func, \
qti_kryo4_gold_core_pwr_dwn, \
CPU_NO_EXTRA1_FUNC, \
cortex_a76_disable_wa_cve_2018_3639, \
cortex_a76_core_pwr_dwn, \
qti_kryo4_gold_cluster_pwr_dwn

14
plat/qti/common/src/aarch64/qti_kryo4_silver.S
View file

@ -22,19 +22,11 @@ func qti_kryo4_silver_reset_func
mov x19, x30
bl qtiseclib_kryo4_silver_reset_asm
ret x19
mov x30, x19
b cortex_a55_reset_func
endfunc qti_kryo4_silver_reset_func
/* ------------------------------------------------------
* The CPU Ops core power down function for Kryo-3 Silver
* ------------------------------------------------------
*/
func qti_kryo4_silver_core_pwr_dwn
ret
endfunc qti_kryo4_silver_core_pwr_dwn
/* ---------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Silver
* ---------------------------------------------------------
@ -75,5 +67,5 @@ endfunc qti_kryo4_silver_cpu_reg_dump
declare_cpu_ops qti_kryo4_silver, QTI_KRYO4_SILVER_MIDR, \
qti_kryo4_silver_reset_func, \
qti_kryo4_silver_core_pwr_dwn, \
cortex_a55_core_pwr_dwn, \
qti_kryo4_silver_cluster_pwr_dwn

14
plat/qti/common/src/aarch64/qti_kryo6_gold.S
View file

@ -28,19 +28,11 @@ func qti_kryo6_gold_reset_func
mov x19, x30
bl qtiseclib_kryo6_gold_reset_asm
ret x19
mov x30, x19
b cortex_a78_reset_func
endfunc qti_kryo6_gold_reset_func
/* ----------------------------------------------------
* The CPU Ops core power down function for Kryo-3 Gold
* ----------------------------------------------------
*/
func qti_kryo6_gold_core_pwr_dwn
ret
endfunc qti_kryo6_gold_core_pwr_dwn
/* -------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Gold
* -------------------------------------------------------
@ -79,5 +71,5 @@ endfunc qti_kryo6_gold_cpu_reg_dump
declare_cpu_ops qti_kryo6_gold, QTI_KRYO6_GOLD_MIDR, \
qti_kryo6_gold_reset_func, \
qti_kryo6_gold_core_pwr_dwn, \
cortex_a78_core_pwr_dwn, \
qti_kryo6_gold_cluster_pwr_dwn

14
plat/qti/common/src/aarch64/qti_kryo6_silver.S
View file

@ -22,19 +22,11 @@ func qti_kryo6_silver_reset_func
mov x19, x30
bl qtiseclib_kryo6_silver_reset_asm
ret x19
mov x30, x19
b cortex_a55_reset_func
endfunc qti_kryo6_silver_reset_func
/* ------------------------------------------------------
* The CPU Ops core power down function for Kryo-3 Silver
* ------------------------------------------------------
*/
func qti_kryo6_silver_core_pwr_dwn
ret
endfunc qti_kryo6_silver_core_pwr_dwn
/* ---------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Silver
* ---------------------------------------------------------
@ -75,5 +67,5 @@ endfunc qti_kryo6_silver_cpu_reg_dump
declare_cpu_ops qti_kryo6_silver, QTI_KRYO6_SILVER_MIDR, \
qti_kryo6_silver_reset_func, \
qti_kryo6_silver_core_pwr_dwn, \
cortex_a55_core_pwr_dwn, \
qti_kryo6_silver_cluster_pwr_dwn

17
plat/qti/common/src/qti_bl31_setup.c
View file

@ -35,17 +35,11 @@ static entry_point_info_t bl33_image_ep_info;
*/
static uint64_t g_qti_cpu_cntfrq;
/*
* Lock variable to serialize cpuss reset execution.
*/
spinlock_t g_qti_cpuss_boot_lock __attribute__ ((section("tzfw_coherent_mem"),
aligned(CACHE_WRITEBACK_GRANULE))) = {0x0};
/*
* Variable to hold bl31 cold boot status. Default value 0x0 means yet to boot.
* Any other value means cold booted.
*/
uint32_t g_qti_bl31_cold_booted __attribute__ ((section("tzfw_coherent_mem"))) = 0x0;
uint32_t g_qti_bl31_cold_booted;
/*******************************************************************************
* Perform any BL31 early platform setup common to ARM standard platforms.
@ -91,13 +85,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
******************************************************************************/
void bl31_plat_arch_setup(void)
{
qti_setup_page_tables(BL_CODE_BASE,
BL_COHERENT_RAM_END - BL_CODE_BASE,
qti_setup_page_tables(
BL31_START,
BL31_END-BL31_START,
BL_CODE_BASE,
BL_CODE_END,
BL_RO_DATA_BASE,
BL_RO_DATA_END,
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
BL_RO_DATA_END
);
enable_mmu_el3(0);
}

13
plat/qti/common/src/qti_common.c
View file

@ -77,13 +77,14 @@ unsigned int plat_qti_my_cluster_pos(void)
* - Read-only data section;
* - Coherent memory region, if applicable.
*/
void qti_setup_page_tables(uintptr_t total_base,
void qti_setup_page_tables(
uintptr_t total_base,
size_t total_size,
uintptr_t code_start,
uintptr_t code_limit,
uintptr_t rodata_start,
uintptr_t rodata_limit,
uintptr_t coh_start, uintptr_t coh_limit)
uintptr_t rodata_limit
)
{
/*
* Map the Trusted SRAM with appropriate memory attributes.
@ -106,12 +107,6 @@ void qti_setup_page_tables(uintptr_t total_base,
mmap_add_region(rodata_start, rodata_start,
rodata_limit - rodata_start, MT_RO_DATA | MT_SECURE);
/* Re-map the coherent memory region */
VERBOSE("Coherent region: %p - %p\n",
(void *)coh_start, (void *)coh_limit);
mmap_add_region(coh_start, coh_start,
coh_limit - coh_start, MT_DEVICE | MT_RW | MT_SECURE);
/* Now (re-)map the platform-specific memory regions */
mmap_add(plat_qti_mmap);

15
plat/qti/qtiseclib/src/qtiseclib_interface_stub.c
View file

@ -49,6 +49,21 @@ void qtiseclib_kryo4_silver_reset_asm(void)
{
}
/*
* Execute CPU (Kryo4 gold) specific reset handler / system initialization.
* This takes care of executing required CPU errata's.
*
* Clobbers: x0 - x16
*/
void qtiseclib_kryo6_gold_reset_asm(void)
{
}
void qtiseclib_kryo6_silver_reset_asm(void)
{
}
/*
* C Api's
*/

19
plat/qti/sc7180/platform.mk
View file

@ -12,12 +12,17 @@ CHIPSET := ${PLAT}
# Turn On Separate code & data.
SEPARATE_CODE_AND_RODATA := 1
USE_COHERENT_MEM := 1
USE_COHERENT_MEM := 0
WARMBOOT_ENABLE_DCACHE_EARLY := 1
HW_ASSISTED_COHERENCY := 1
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
#Enable errata for cortex_a55 and cortex_a76
ERRATA_A55_1530923 := 1
ERRATA_A76_1165522 := 1
# Enable PSCI v1.0 extended state ID format
PSCI_EXTENDED_STATE_ID := 1
ARM_RECOM_STATE_ID_ENC := 1
@ -93,10 +98,14 @@ TIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \
GIC_SOURCES := plat/common/plat_gicv3.c \
${GICV3_SOURCES} \
BL31_SOURCES += ${QTI_BL31_SOURCES} \
${PSCI_SOURCES} \
${GIC_SOURCES} \
${TIMER_SOURCES} \
CPU_SOURCES := lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/cortex_a55.S \
BL31_SOURCES += ${QTI_BL31_SOURCES} \
${PSCI_SOURCES} \
${GIC_SOURCES} \
${TIMER_SOURCES} \
${CPU_SOURCES} \
LIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET}

21
plat/qti/sc7280/platform.mk
View file

@ -12,8 +12,15 @@ CHIPSET := ${PLAT}
# Turn On Separate code & data.
SEPARATE_CODE_AND_RODATA := 1
USE_COHERENT_MEM := 1
USE_COHERENT_MEM := 0
WARMBOOT_ENABLE_DCACHE_EARLY := 1
HW_ASSISTED_COHERENCY := 1
#Enable errata configs for cortex_a78 and cortex_a55
ERRATA_A55_1530923 := 1
ERRATA_A78_1941498 := 1
ERRATA_A78_1951500 := 1
ERRATA_A78_2132060 := 1
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
@ -93,10 +100,14 @@ TIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \
GIC_SOURCES := plat/common/plat_gicv3.c \
${GICV3_SOURCES} \
BL31_SOURCES += ${QTI_BL31_SOURCES} \
${PSCI_SOURCES} \
${GIC_SOURCES} \
${TIMER_SOURCES} \
CPU_SOURCES := lib/cpus/aarch64/cortex_a78.S \
lib/cpus/aarch64/cortex_a55.S \
BL31_SOURCES += ${QTI_BL31_SOURCES} \
${PSCI_SOURCES} \
${GIC_SOURCES} \
${TIMER_SOURCES} \
${CPU_SOURCES} \
LIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET}