Tentatively updating the plan for TF-A v2.13 release in May'25.
Change-Id: I98abe5f72901b71179a1efe3762046756d5ab6ac
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Add required SMCs by RMM to push attestation signing requests to EL3
and get responses. EL3 may then choose to push these requests to a HES
as suitable for a platform. This patch also supports the new
RMM_EL3_FEATURES interface, that RMM can use to query for support for
HES based signing. The new interface exposes a feature register with
different bits defining different discoverable features. This new
interface is available starting the 0.4 version of the RMM-EL3
interface, causing the version to bump up. This patch also adds a
platform port for FVP that implements the platform hooks required to
enable the new SMCs, but it does not push to a HES and instead copies a
zeroed buffer in EL3.
Change-Id: I69c110252835122a9533e71bdcce10b5f2a686b2
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>
None console does not register boot and runtime console.
User will not observe any console logs.
Change-Id: I39877c900f399ae7cffc1bb599b30c7a23888fc8
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
Modified platform.mk and bl31_setup to
invoke setup_console and runtime_console
to support dtb console parsing and runtime.
Change-Id: I68c2fffd90e38274cfad4f85dd51c722fae0ee89
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
In the platform.mk file, new console types named dtb
are to be created a macro, VERSAL_NET_CONSOLE_ID_dtb, will
be introduced to check DT console.Users will have the
option to select VERSAL_NET_CONSOLE to dtb, which will run
from the DDR address and OCM. The address XILINX_OF_BOARD_DTB_ADDR
needs to be provided. This configuration will register the
DT console in TF-A
Change-Id: I530492c3f48705387e50895aef4bf229a82d350d
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
Introduce a build-time parameter (CONSOLE_RUNTIME) to select
separate runtime console options. For boot-time console, remove
the runtime flag and add a boot/crash flag. Additionally,
introduce an RT_CONSOLE_IS macro to check different UART types.
Implement a common function, console_runtime_init(), to initialize
the runtime console. Ensure that all platforms have access to
this feature.
The current implementation utilizes a single console for boot,
crash, and runtime. Make sure that the dedicated console integrates
into runtime and crash scenarios
Change-Id: I49b8554c0f067c85eb693e039a0cf17c5e6794ce
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
In the platform.mk file, new console types named dtb
are to be created a macro, VERSAL_CONSOLE_ID_dtb, will
be introduced to check DT console.Users will have the
option to select VERSAL_CONSOLE to dtb, which will run
from the DDR address and OCM. The address XILINX_OF_BOARD_DTB_ADDR
needs to be provided. This configuration will register the
DT console in TF-A.
Change-Id: Iee0ed2d5bb73c833f34809699203622b912cdbd7
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
Introduce a build-time parameter (CONSOLE_RUNTIME) to select
separate runtime console options. For boot-time console, remove
the runtime flag and add a boot/crash flag. Additionally,
introduce an RT_CONSOLE_IS macro to check different UART types.
Implement a common function, console_runtime_init(), to initialize
the runtime console. Ensure that all platforms have access to
this feature.
The current implementation utilizes a single console for boot,
crash, and runtime. Make sure that the dedicated console integrates
into runtime and crash scenarios.
Change-Id: I7b71fb4a8cd36e8e91c98ebee09904ba47222e33
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
Refactored register_console using console holder structure as
input. Structure holds console scope and console type as additional
members. These modifications enhance code readability and
maintainability, contributing to a clearer and more sustainable
codebase for future development.
Change-Id: I7fcc1accfdecdacc205d427a80031536c456638e
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
In the platform.mk file, new console types named dtb are to be created
a macro, ZYNQMP_CONSOLE_ID_dtb, will be introduced to check DT console.
Users will have the option to select ZYNQMP_CONSOLE to dtb, which will
run from the DDR address. The address XILINX_OF_BOARD_DTB_ADDR needs
to be provided. This configuration will register the DT console in TF-A.
Flags for the ZynqMP platform and other AMD-Xilinx platforms will be
updated to utilize common code.
Change-Id: If74da4a80196575335c9d5562e6d8cd12d99561c
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
Introduce a build-time parameter (CONSOLE_RUNTIME) to select
separate runtime console options. For boot-time console, remove
the runtime flag and add a boot/crash flag. Additionally,
introduce an RT_CONSOLE_IS macro to check different UART types.
Implement a common function, console_runtime_init(), to initialize
the runtime console. Ensure that all platforms have access to
this feature.
The current implementation utilizes a single console for boot,
crash, and runtime. Make sure that the dedicated console integrates
into runtime and crash scenarios.
Change-Id: I32913dede3d87109e54d179e7d99f45c33b9097b
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
DCC driver to support boot and runtime console scope
switch for dedicated boot and runtime consoles.
Change-Id: I7769dc44860a5fda99ca42ce17a3a6009288d7e7
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
Arm v8.9 introduces FEAT_SCTLR2, adding SCTLR2_ELx registers.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.
Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.
Change-Id: I0c4cba86917b6b065a7e8dd6af7daf64ee18dcda
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Arm v8.9 introduces FEAT_THE, adding Translation Hardening Extension
Read-Check-Write mask registers, RCWMASK_EL1 and RCWSMASK_EL1.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.
Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.
Change-Id: I8775787f523639b39faf61d046ef482f73b2a562
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Update the UFS clock rates as per the expected range
- Update the clock rates of "ufs_phy_clk" and "ufs_ref_pclk" to 26MHz
as 100MHz is not the valid clock rate for these two clocks.
- cpu_clock rate (908KHz) is not valid clock for UFS, hence skip setting
up UFS clocks to cpu_clock for SPP platform.
Change-Id: I31863619ca1bd527df283d1636493dd8fce18809
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Now that DDR is initialized, we can load the different firmware
parts: BL32 (OP-TEE header), BL32 extra1 (OP-TEE), HW_CONFIG (U-Boot
device tree) and BL33 (U-Boot).
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic79429c3bd4516c339f91a10e0b3f2828bf6c392
Move the flash address to its own devicetree node in
tc_spmc_manifest.dtsi. This patch also changes the device-type to
ns-device-memory which is the correct type for a flash device.
Change-Id: I19503ac35c433661faaaa01c0b83a16540d73810
Co-developed-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Address issue CID 445362 and CID 445361 found during coverity scan.
Change-Id: I1ab460d2e1353b81517788e32de662f203b0352f
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Add include for DDR configuration, and reference to OTP storing the
board ID.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie2d5272ecf1dac77b91b2c148ec4dc1fb7b76631
These DT files will be used by STM32MP2 boards. They embed DDR parameters
for DDR4 2x8Gb 2*16bits, at 800MHz or 1200MHz.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iec73f9c5028f897624125082bdb591274aad3afc
Complete DDR node with all necessary DDRCTRL (register values) and
DDRPHY (user input values) settings.
Add also name and speed properties.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ie63f48dcacefe590c68cf6ec694d9e82349cece8
Add the required power supplies for DDR nodes. The power supplies are
provided by STPMIC2 regulators.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I951da75a554bc4fbfbc69ea9cd1171d99ed7ce46
Call stm32mp2_ddr_probe() function in platform setup.
Move DDR systematic test file in common.mk.
Change-Id: I982abd33635a3222a52c967eac64676bc26b0d6b
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY
and its firmware, as well as the DDR controller.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5
Arm has made the strategic decision to deprecate the TC2 platform. As
a result, software development and the creation of fast models for TC2
have been officially discontinued. The TC2 platform, now considered
obsolete, has been succeeded by the TC3 and TC4 platforms. Notably,
both TC3 and TC4 are already integrated into TF-A, with TC3 included
in the CI repository. Work to add CI support for TC4 is currently in
progress.
Change-Id: I4df3c3e947faa1849a0f4742593c604cb2ee43b9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the first core in isolation
to avoid crashes due to cache invalidation operations. Later,
it will disable the isolation and reconfigure the module every
time a new core is added or removed through PSCI.
Change-Id: Ida42db91b10be1e66c3b9b73674d1e37a61844dd
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.
Change-Id: I3e4205171d9356190b60498cae322318520bb1c2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
