CBOR encoding in the platform test requires
a slightly bigger stack, so increase it with 0x100 bytes.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I1b151aa29b3ccfcefa733d189d7aab88653cef1f
The delegated attestation service was updated to be
aligned with RMM spec 1.0-rel0-rc2 version. The test
suite uses the QCBOR library to encode the public key
to be a CBOR serialized COSE_Key object.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ib9e1d80f7b4bca8783ae1f7cf4567725c2aa8538
With the updated firmware update implementation in the Trusted Services,
it is no longer needed to carve out static memory. Memory will be
allocated dynamically in U-Boot and shared with the firmware update
secure partition of Trusted Services.
Change-Id: I0fb128a458773236ee10526edfa1116b229e4d6e
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
The non-secure (NS) timer in TC is AP_GTCLK_NS_CNTBase1. This commit
corrects the NS frame ID from its original value of 0 to U(1),
ensuring that the correct CNTACR register bits are written.
This change enables access to the counter registers.
Change-Id: I287ab9c373a60741f78d44a67f546326916473ea
Signed-off-by: Sandeep Chiluvuru <sandeep.chiluvuru@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Due to change [1], the FIP tool was compiled with the default platform
instead of the one specified via the command line, as make_helpers.mk
set the PLAT option to default. This happened because the root Makefile
invoked FIP tool compilation without the PLAT option. The issue has
been fixed by explicitly providing the PLAT option for FIP tool
compilation.
[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/26597
Change-Id: Icc516f8d44706df03c7e6ee123b58afeda72cea7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Apply the mitigation only for the revision and variant
mentioned in the SDEN.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN859515/latest
Change-Id: Ifda1f4cb32bdec9a9af29397ddc03bf22a7a87fc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
The code in dt_console_init() has been refactored into multiple
functions to establish a more generic approach for retrieving UART
information from DT. These modifications enhance code readability
and maintainability, contributing to a clearer and more sustainable
codebase for future development.
Change-Id: I877b7ae484bbf2f5919f3c79e5ae650bb93e3037
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
The setup_runtime_console() function is renamed to register_console()
for the purpose of reusing it in the registration of the console.
Change-Id: I6b340423169aa6794d07502dadab65c3f0209339
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Updates variable names to follow a more consistent
and descriptive naming.
These changes improve code readability and maintainability, making
the codebase more understandable and maintainable for future
development.
Change-Id: I3fff8fe371f9d4d3489ffe62cbf721381403fef5
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Renames the runtime_console_init() function to dt_console_init()
for better naming clarity.
Change-Id: I7f6d80ce23307d57e09c613be48482d49d6ad45b
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Disabling AXI port, enabling host interface and both enabling/disabling
software self-refresh services are already present inside the driver
source code.
Factorize by gathering them as services inside the generic part,
and adapt driver to call these new functions.
Add services to manage quasi-dynamic registers. DDRCTRL contains
quasi-dynamic registers, which are dynamic only under some conditions
defined by the user guide (with 4 groups).
In our driver, out of reset state, only groups 3 and 4 are updated.
Group 4 needs only sw_done/sw_done_ack sequence, already available.
Group 3 sequence include more conditions, that are gathered in
specific services. stm32mp_ddr_disable_host_interface() has been added
to do this.
Add dedicated generic service to toggle rfshctl3.refresh_update_level
and wait for completion.
Manage AXI ports and HIF when updating QD3 registers. Quasi-dynamic
group 3 (QD3) registers are updated when DDR is not completely
initialized, i.e. when AXI ports are not enabled and possibly when
host interface (HIF) is not enabled too.
In that case, a specific mechanism is necessary to restore the same
conditions as before accessing QD3 registers.
Static functions have been added to get AXI ports and HIF states and
are used to determine the needed conditions to set/unset.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I880f88b1cb6fc76199ad9ea33e9d63a5c469aed4
It was only used for an error trace, with little added value. This
allows some gains in DDR driver data size.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I02e2fc75efd90ff188e62f39850b9bd4c3af1649
Instead of using hard-coded number in DDR driver, use macros.
Modify TIMEOUT_US_1S to DDR_TIMEOUT_US_1S to align with other defines.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I489084132821774b0049a4a5d7fc30db24a7bb11
This function is used to know if this is a return from Standby mode,
and the DDR was in self-refresh, allowing a correct return to OS.
They just return false for the moment.
Change-Id: Ie7de9a9f6477f8158e144f6626070a77fdc53ceb
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Add RETRAM base address and size definition at platform level.
RETRAM is used by the DDR driver to store retention registers (DDR
training results) in order to restore them in standby exit sequence.
Add map/unmap services at platform level and configure dedicated RISAB5.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I460b36fccce62e83c1fbff298f96b23530aaa4f3
Add a function to get DDRDBG peripheral IO memory base address.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I20d14fca49528c296c1f7d49a66129d932f44e49
Modify platform driver to handle the DDR power supplies when
a PMIC is present.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I98df132a63c2ad351d4dae949f5dbb831cc40637
Modify the DDR driver to handle the DDR power supplies when a PMIC
is present in the function stm32mp_board_ddr_power_init(), define
in the platform file.
This patch allows to easily modify the used DDR power supplies
for customer boards, when they don't use STPMIC1 PMU or when
the regulators are not connected as on the STMicroelectronics
boards.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I93ee6295ef7032ac20f03608d22cd460f7d87ef5
This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.
Change-Id: Iee222595962273913a570786ff1df5dc3ad328df
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.
Change-Id: I20ef3be35f88649979d577ec8be4357813d4c1b7
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.
Change-Id: If3507f812ed4cfa518e6f5c5de977a76713fafd8
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.
Change-Id: I1d369d977e0f2749024736d53fbb5c7d5555f6cb
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.
Change-Id: I435dbcbe1c4aad7c69eb49599cd0dbca0677150d
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
The digest size in bytes for sha1/256/384/512 were defined in multiple
places. Refactor the macros into a common header file.
Change-Id: I84ef3561486ff70345ae8c871d5d6e1564574ec2
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>
Updating toolchain to the latest production release version
13.3.Rel1 publicly available on:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads
We build TF-A in CI using x86_64 Linux hosted cross toolchains:
---------------------------------------------------------------
* AArch32 bare-metal target (arm-none-eabi)
* AArch64 bare-metal target (aarch64-none-elf)
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: If5915fdc14a6c65ce58ac7fccfddd6fe85c0d7c9
Cortex-X4 erratum 3076789 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.
The workaround is to set chicken bits CPUACTLR3_EL1[14:13]=0b11
and CPUACTLR_EL1[52] = 1.
Expected performance degradation is < 0.5%, but isolated
benchmark components might see higher impact.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest
Change-Id: Ib100bfab91efdb6330fdcdac127bcc5732d59196
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
The function 'update_stack_depth' modifies the value of the 'depth'
parameter passed by reference. Typically, the caller recevies this
parameter by value, and it is then passed to 'update_stack_depth' by
reference. This violates MISRA 17.8 rule. To address this issue, a new
local variable is introduced to store the value of 'depth'.
Change-Id: Ia37f4ede9e6558f778bdda17b7b195f1f50d0c30
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.
Change-Id: Idfed24b3e74a189df87f9782886a91b906cd2022
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition 0, is also connected to this IP block. Therefore, all the
dependencies mentioned above must be configured to have a working clock.
Change-Id: Ia841428db9acb95c59ea851b6afeb0b7ff9230a2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.
Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
MC_ME is one of the leading hardware blocks responsible for partitions'
transition to and from a reset state. Not being the only one involved in
this role, it must cooperate with some other modules (MC_RGM, RDC) to
successfully bring a peripheral out of the reset state. As a result, the
partition management is isolated into a dedicated file, as parts of it
will later contribute to peripheral reset control.
Change-Id: I6a9dbf28008b1677bc847bbafa474b489c999d05
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
MC_RGM is a hardware block involved in resetting peripherals and
partitions. Here, the accessories for partition reset are added.
Change-Id: If00755fe0e93ba2e4841f95ed5ae3c87db20bebf
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The S32CC-based SoCs are organized in partitions. These are
software-resettable domains in which configuration participates in
MC_CGM, MC_ME, and RDC modules. A partition is an island that may
contain multiple blocks, each of which corresponds to a peripheral or a
core and can, in most cases, be reset individually. This reset structure
results in better device availability. If a fault is detected in a
software reset domain, that domain can be reset separately without
impacting the operation of the rest of the chip.
Change-Id: Ie60dbe151309209e377aa71356dbbd6a4f376a8c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
In this commit, Trusted Board Boot has been enabled for the RD-1 AE
platform, and the non-volatile counter remains at the default
values since the non-volatile counter is read-only for Arm
development platforms.
Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: I2e1072101e56da0e474d2a3e9802e5d65a77fd55
This commit introduces BL31 to the RD-1 AE platform. The RD-1 AE
platform incorporates an SCP for CPU power control.
Additinaly introducing the memory descriptor provides BL image
information that gets used by BL2 to load the images
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: I035cbfd09f254aa47483ad35676f1cb3ffb661bd
Create a new platform for the RD-1 AE automotive FVP.
This platform contains:
* Neoverse-V3AE, Arm9.2-A application processor
* A GICv4-compatible GIC-720AE
* 128 MB of SRAM, of which 1 MB is reserved for TF-A
and BL2 runs at ELmax (EL3).
Additionally, this commit updates the maintainers.rst file and
the changelog.yaml to add scope for RD-1 AE variants.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Signed-off-by: Divin Raj <divin.raj@arm.com>
Signed-off-by: Rahul Singh <rahul.singh@arm.com>
Change-Id: I9ae64b3f05a52653ebd1d334b15b7f21821264e2
