mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
Merge "fix(intel): update CCU configuration for Agilex5 platform" into integration
This commit is contained in:
Mark Dykes
TrustedFirmware Code Review
commit
5d38dc09eb
2 changed files with 767 additions and 254 deletions
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@ -10,6 +10,7 @@
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#include <platform_def.h>
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#include "ncore_ccu.h"
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#include "socfpga_mailbox.h"
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#include "socfpga_plat_def.h"
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#include "socfpga_system_manager.h"
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@ -17,6 +18,486 @@ uint32_t poll_active_bit(uint32_t dir);
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#define SMMU_DMI 1
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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ncore_ccu_reg_t ncore_ccu_modules[] = {
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{"caiu0@1c000000", 0x1C000000, 0x00001000},
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{"ncaiu0@1c001000", 0x1C001000, 0x00001000},
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{"ncaiu1@1c002000", 0x1C002000, 0x00001000},
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{"ncaiu2@1c003000", 0x1C003000, 0x00001000},
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{"ncaiu3@1c004000", 0x1C004000, 0x00001000},
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{"dce0@1c005000", 0x1C005000, 0x00001000},
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{"dce1@1c006000", 0x1C006000, 0x00001000},
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{"dmi0@1c007000", 0x1C007000, 0x00001000},
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{"dmi1@1c008000", 0x1C008000, 0x00001000},
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{"noc_fw_l4_per@10d21000", 0x10D21000, 0x0000008C},
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{"noc_fw_l4_sys@10d21100", 0x10D21100, 0x00000098},
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{"noc_fw_lwsoc2fpga@10d21300", 0x10D21300, 0x00000004},
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{"noc_fw_soc2fpga@10d21200", 0x10D21200, 0x00000004},
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{"noc_fw_tcu@10d21400", 0x10D21400, 0x00000004}
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};
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ncore_ccu_t ccu_caiu0[] = {
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/* CAIUAMIGR */
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{0x000003C0, 0x00000003, 0x0000001F},
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/* CAIUMIFSR */
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{0x000003C4, 0x00000000, 0x07070777},
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/* DII1_MPFEREGS */
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{0x00000414, 0x00018000, 0xFFFFFFFF},
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{0x00000418, 0x00000000, 0x000000FF},
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{0x00000410, 0xC0E00200, 0xC1F03E1F},
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/* DII2_GICREGS */
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{0x00000424, 0x0001D000, 0xFFFFFFFF},
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{0x00000428, 0x00000000, 0x000000FF},
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{0x00000420, 0xC0800400, 0xC1F03E1F},
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/* NCAIU0_LWSOC2FPGA */
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{0x00000444, 0x00020000, 0xFFFFFFFF},
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{0x00000448, 0x00000000, 0x000000FF},
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{0x00000440, 0xC1100006, 0xC1F03E1F},
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/* NCAIU0_SOC2FPGA_1G */
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{0x00000454, 0x00040000, 0xFFFFFFFF},
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{0x00000458, 0x00000000, 0x000000FF},
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{0x00000450, 0xC1200006, 0xC1F03E1F},
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/* DMI_SDRAM_2G */
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{0x00000464, 0x00080000, 0xFFFFFFFF},
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{0x00000468, 0x00000000, 0x000000FF},
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{0x00000460, 0x81300006, 0xC1F03E1F},
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/* NCAIU0_SOC2FPGA_16G */
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{0x00000474, 0x00400000, 0xFFFFFFFF},
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{0x00000478, 0x00000000, 0x000000FF},
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{0x00000470, 0xC1600006, 0xC1F03E1F},
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/* DMI_SDRAM_30G */
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{0x00000484, 0x00800000, 0xFFFFFFFF},
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{0x00000488, 0x00000000, 0x000000FF},
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{0x00000480, 0x81700006, 0xC1F03E1F},
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/* NCAIU0_SOC2FPGA_256G */
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{0x00000494, 0x04000000, 0xFFFFFFFF},
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{0x00000498, 0x00000000, 0x000000FF},
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{0x00000490, 0xC1A00006, 0xC1F03E1F},
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/* DMI_SDRAM_480G */
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{0x000004A4, 0x08000000, 0xFFFFFFFF},
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{0x000004A8, 0x00000000, 0x000000FF},
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{0x000004A0, 0x81B00006, 0xC1F03E1F}
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};
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ncore_ccu_t ccu_ncaiu0[] = {
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/* NCAIU0AMIGR */
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{0x000003C0, 0x00000003, 0x0000001F},
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/* NCAIU0MIFSR */
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{0x000003C4, 0x00000000, 0x07070777},
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/* PSS */
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{0x00000404, 0x00010000, 0xFFFFFFFF},
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{0x00000408, 0x00000000, 0x000000FF},
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{0x00000400, 0xC0F00000, 0xC1F03E1F},
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/* DII1_MPFEREGS */
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{0x00000414, 0x00018000, 0xFFFFFFFF},
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{0x00000418, 0x00000000, 0x000000FF},
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{0x00000410, 0xC0E00200, 0xC1F03E1F},
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/* NCAIU0_LWSOC2FPGA */
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{0x00000444, 0x00020000, 0xFFFFFFFF},
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{0x00000448, 0x00000000, 0x000000FF},
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{0x00000440, 0xC1100006, 0xC1F03E1F},
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/* NCAIU0_SOC2FPGA_1G */
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{0x00000454, 0x00040000, 0xFFFFFFFF},
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{0x00000458, 0x00000000, 0x000000FF},
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{0x00000450, 0xC1200006, 0xC1F03E1F},
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/* DMI_SDRAM_2G */
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{0x00000464, 0x00080000, 0xFFFFFFFF},
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{0x00000468, 0x00000000, 0x000000FF},
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{0x00000460, 0x81300006, 0xC1F03E1F},
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/* NCAIU0_SOC2FPGA_16G */
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{0x00000474, 0x00400000, 0xFFFFFFFF},
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{0x00000478, 0x00000000, 0x000000FF},
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{0x00000470, 0xC1600006, 0xC1F03E1F},
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/* DMI_SDRAM_30G */
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{0x00000484, 0x00800000, 0xFFFFFFFF},
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{0x00000488, 0x00000000, 0x000000FF},
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{0x00000480, 0x81700006, 0xC1F03E1F},
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/* NCAIU0_SOC2FPGA_256G */
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{0x00000494, 0x04000000, 0xFFFFFFFF},
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{0x00000498, 0x00000000, 0x000000FF},
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{0x00000490, 0xC1A00006, 0xC1F03E1F},
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/* DMI_SDRAM_480G */
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{0x000004A4, 0x08000000, 0xFFFFFFFF},
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{0x000004A8, 0x00000000, 0x000000FF},
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{0x000004A0, 0x81B00006, 0xC1F03E1F}
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};
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ncore_ccu_t ccu_ncaiu1[] = {
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/* NCAIU1AMIGR */
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{0x000003C0, 0x00000003, 0x0000001F},
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/* NCAIU1MIFSR */
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{0x000003C4, 0x00000000, 0x07070777},
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/* DMI_SDRAM_2G */
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{0x00000464, 0x00080000, 0xFFFFFFFF},
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{0x00000468, 0x00000000, 0x000000FF},
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{0x00000460, 0x81300006, 0xC1F03E1F},
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/* DMI_SDRAM_30G */
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{0x00000484, 0x00800000, 0xFFFFFFFF},
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{0x00000488, 0x00000000, 0x000000FF},
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{0x00000480, 0x81700006, 0xC1F03E1F},
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/* DMI_SDRAM_480G */
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{0x000004A4, 0x08000000, 0xFFFFFFFF},
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{0x000004A8, 0x00000000, 0x000000FF},
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{0x000004A0, 0x81B00006, 0xC1F03E1F}
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};
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ncore_ccu_t ccu_ncaiu2[] = {
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/* NCAIU2AMIGR */
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{0x000003C0, 0x00000003, 0x0000001F},
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/* NCAIU2MIFSR */
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{0x000003C4, 0x00000000, 0x07070777},
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/* DMI_SDRAM_2G */
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{0x00000464, 0x00080000, 0xFFFFFFFF},
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{0x00000468, 0x00000000, 0x000000FF},
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{0x00000460, 0x81300006, 0xC1F03E1F},
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/* DMI_SDRAM_30G */
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{0x00000484, 0x00800000, 0xFFFFFFFF},
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{0x00000488, 0x00000000, 0x000000FF},
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{0x00000480, 0x81700006, 0xC1F03E1F},
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/* DMI_SDRAM_480G */
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{0x000004A4, 0x08000000, 0xFFFFFFFF},
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{0x000004A8, 0x00000000, 0x000000FF},
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{0x000004A0, 0x81B00006, 0xC1F03E1F}
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};
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ncore_ccu_t ccu_ncaiu3[] = {
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/* NCAIU3AMIGR */
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{0x000003C0, 0x00000003, 0x0000001F},
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/* NCAIU3MIFSR */
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{0x000003C4, 0x00000000, 0x07070777},
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/* DII1_MPFEREGS */
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{0x00000414, 0x00018000, 0xFFFFFFFF},
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{0x00000418, 0x00000000, 0x000000FF},
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{0x00000410, 0xC0E00200, 0xC1F03E1F},
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/* DMI_SDRAM_2G */
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{0x00000464, 0x00080000, 0xFFFFFFFF},
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{0x00000468, 0x00000000, 0x000000FF},
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{0x00000460, 0x81300006, 0xC1F03E1F},
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/* DMI_SDRAM_30G */
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{0x00000484, 0x00800000, 0xFFFFFFFF},
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{0x00000488, 0x00000000, 0x000000FF},
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{0x00000480, 0x81700006, 0xC1F03E1F},
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/* DMI_SDRAM_480G */
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{0x000004A4, 0x08000000, 0xFFFFFFFF},
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{0x000004A8, 0x00000000, 0x000000FF},
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{0x000004A0, 0x81B00006, 0xC1F03E1F}
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};
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ncore_ccu_t ccu_dce0[] = {
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/* DCEUAMIGR0 */
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{0x000003C0, 0x00000003, 0x0000001F},
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/* DCEUMIFSR0 */
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{0x000003C4, 0x00000000, 0x07070777},
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/* DMI_SDRAM_2G */
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{0x00000464, 0x00080000, 0xFFFFFFFF},
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{0x00000468, 0x00000000, 0x000000FF},
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{0x00000460, 0x81300006, 0xC1F03E1F},
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/* DMI_SDRAM_30G */
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{0x00000484, 0x00800000, 0xFFFFFFFF},
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{0x00000488, 0x00000000, 0x000000FF},
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{0x00000480, 0x81700006, 0xC1F03E1F},
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/* DMI_SDRAM_480G */
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{0x000004A4, 0x08000000, 0xFFFFFFFF},
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{0x000004A8, 0x00000000, 0x000000FF},
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{0x000004A0, 0x81B00006, 0xC1F03E1F}
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};
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ncore_ccu_t ccu_dce1[] = {
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/* DCEUAMIGR1 */
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{0x000003C0, 0x00000003, 0x0000001F},
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/* DCEUMIFSR1 */
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{0x000003C4, 0x00000000, 0x07070777},
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/* DMI_SDRAM_2G */
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{0x00000464, 0x00080000, 0xFFFFFFFF},
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{0x00000468, 0x00000000, 0x000000FF},
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{0x00000460, 0x81300006, 0xC1F03E1F},
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/* DMI_SDRAM_30G */
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{0x00000484, 0x00800000, 0xFFFFFFFF},
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{0x00000488, 0x00000000, 0x000000FF},
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{0x00000480, 0x81700006, 0xC1F03E1F},
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/* DMI_SDRAM_480G */
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{0x000004A4, 0x08000000, 0xFFFFFFFF},
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{0x000004A8, 0x00000000, 0x000000FF},
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{0x000004A0, 0x81B00006, 0xC1F03E1F}
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};
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ncore_ccu_t ccu_dmi0[] = {
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/* DMIUSMCTCR */
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{0x00000300, 0x00000001, 0x00000003},
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{0x00000300, 0x00000003, 0x00000003}
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};
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ncore_ccu_t ccu_dmi1[] = {
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/* DMIUSMCTCR */
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{0x00000300, 0x00000001, 0x00000003},
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{0x00000300, 0x00000003, 0x00000003}
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};
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ncore_ccu_t ccu_noc_fw_l4_per[] = {
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/* NAND */
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{0x00000000, 0x01010001, 0x01010001},
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/* USB0 */
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{0x0000000C, 0x01010001, 0x01010001},
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/* USB1 */
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{0x00000010, 0x01010001, 0x01010001},
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/* SPI_MAIN0 */
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{0x0000001C, 0x01010301, 0x01010301},
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/* SPI_MAIN1 */
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{0x00000020, 0x01010301, 0x01010301},
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/* SPI_SECONDARY0 */
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{0x00000024, 0x01010301, 0x01010301},
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/* SPI_SECONDARY1 */
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{0x00000028, 0x01010301, 0x01010301},
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/* EMAC0 */
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{0x0000002C, 0x01010001, 0x01010001},
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/* EMAC1 */
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{0x00000030, 0x01010001, 0x01010001},
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/* EMAC2 */
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{0x00000034, 0x01010001, 0x01010001},
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/* SDMMC */
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{0x00000040, 0x01010001, 0x01010001},
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/* GPIO0 */
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{0x00000044, 0x01010301, 0x01010301},
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/* GPIO1 */
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{0x00000048, 0x01010301, 0x01010301},
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/* I2C0 */
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{0x00000050, 0x01010301, 0x01010301},
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/* I2C1 */
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{0x00000054, 0x01010301, 0x01010301},
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/* I2C2 */
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{0x00000058, 0x01010301, 0x01010301},
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/* I2C3 */
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{0x0000005C, 0x01010301, 0x01010301},
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/* I2C4 */
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{0x00000060, 0x01010301, 0x01010301},
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/* SP_TIMER0 */
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{0x00000064, 0x01010301, 0x01010301},
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/* SP_TIMER1 */
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{0x00000068, 0x01010301, 0x01010301},
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/* UART0 */
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{0x0000006C, 0x01010301, 0x01010301},
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/* UART1 */
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{0x00000070, 0x01010301, 0x01010301},
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/* I3C0 */
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{0x00000074, 0x01010301, 0x01010301},
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/* I3C1 */
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{0x00000078, 0x01010301, 0x01010301},
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/* DMA0 */
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{0x0000007C, 0x01010001, 0x01010001},
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/* DMA1 */
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{0x00000080, 0x01010001, 0x01010001},
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/* COMBO_PHY */
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{0x00000084, 0x01010001, 0x01010001},
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/* NAND_SDMA */
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{0x00000088, 0x01010301, 0x01010301}
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};
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ncore_ccu_t ccu_noc_fw_l4_sys[] = {
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/* DMA_ECC */
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{0x00000008, 0x01010001, 0x01010001},
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/* EMAC0RX_ECC */
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{0x0000000C, 0x01010001, 0x01010001},
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/* EMAC0TX_ECC */
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{0x00000010, 0x01010001, 0x01010001},
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/* EMAC1RX_ECC */
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{0x00000014, 0x01010001, 0x01010001},
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/* EMAC1TX_ECC */
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{0x00000018, 0x01010001, 0x01010001},
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/* EMAC2RX_ECC */
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{0x0000001C, 0x01010001, 0x01010001},
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/* EMAC2TX_ECC */
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{0x00000020, 0x01010001, 0x01010001},
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/* NAND_ECC */
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{0x0000002C, 0x01010001, 0x01010001},
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/* NAND_READ_ECC */
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{0x00000030, 0x01010001, 0x01010001},
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/* NAND_WRITE_ECC */
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{0x00000034, 0x01010001, 0x01010001},
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/* OCRAM_ECC */
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{0x00000038, 0x01010001, 0x01010001},
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/* SDMMC_ECC */
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{0x00000040, 0x01010001, 0x01010001},
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/* USB0_ECC */
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{0x00000044, 0x01010001, 0x01010001},
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/* USB1_CACHEECC */
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{0x00000048, 0x01010001, 0x01010001},
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/* CLOCK_MANAGER */
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{0x0000004C, 0x01010001, 0x01010001},
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/* IO_MANAGER */
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{0x00000054, 0x01010001, 0x01010001},
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/* RESET_MANAGER */
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{0x00000058, 0x01010001, 0x01010001},
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/* SYSTEM_MANAGER */
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{0x0000005C, 0x01010001, 0x01010001},
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/* OSC0_TIMER */
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{0x00000060, 0x01010301, 0x01010301},
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/* OSC1_TIMER0*/
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{0x00000064, 0x01010301, 0x01010301},
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/* WATCHDOG0 */
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{0x00000068, 0x01010301, 0x01010301},
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/* WATCHDOG1 */
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{0x0000006C, 0x01010301, 0x01010301},
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/* WATCHDOG2 */
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{0x00000070, 0x01010301, 0x01010301},
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/* WATCHDOG3 */
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{0x00000074, 0x01010301, 0x01010301},
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/* DAP */
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{0x00000078, 0x03010001, 0x03010001},
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/* WATCHDOG4 */
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{0x0000007C, 0x01010301, 0x01010301},
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/* POWER_MANAGER */
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{0x00000080, 0x01010001, 0x01010001},
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/* USB1_RXECC */
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{0x00000084, 0x01010001, 0x01010001},
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/* USB1_TXECC */
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{0x00000088, 0x01010001, 0x01010001},
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/* L4_NOC_PROBES */
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{0x00000090, 0x01010001, 0x01010001},
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||||
/* L4_NOC_QOS */
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{0x00000094, 0x01010001, 0x01010001}
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};
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ncore_ccu_t ccu_noc_fw_lwsoc2fpga[] = {
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/* LWSOC2FPGA_CSR */
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{0x00000000, 0x0FFE0301, 0x0FFE0301}
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};
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ncore_ccu_t ccu_noc_fw_soc2fpga[] = {
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/* SOC2FPGA_CSR */
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{0x00000000, 0x0FFE0301, 0x0FFE0301}
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||||
};
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ncore_ccu_t ccu_noc_fw_tcu[] = {
|
||||
/* TCU_CSR */
|
||||
{0x00000000, 0x01010001, 0x01010001}
|
||||
};
|
||||
|
||||
uint32_t init_ncore_ccu(void)
|
||||
{
|
||||
ncore_ccu_t *ccu_module_table = NULL;
|
||||
uint32_t base;
|
||||
uint32_t size;
|
||||
uint32_t val;
|
||||
uint32_t offset;
|
||||
uint32_t mask;
|
||||
uint32_t set_mask = 0U;
|
||||
uint32_t reg = 0U;
|
||||
|
||||
for (int index = 0; index < ARRAY_SIZE(ncore_ccu_modules); index++) {
|
||||
base = ncore_ccu_modules[index].base;
|
||||
size = ncore_ccu_modules[index].size;
|
||||
|
||||
switch (index) {
|
||||
case 0:
|
||||
ccu_module_table = ccu_caiu0;
|
||||
size = (sizeof(ccu_caiu0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
ccu_module_table = ccu_ncaiu0;
|
||||
size = (sizeof(ccu_ncaiu0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
ccu_module_table = ccu_ncaiu1;
|
||||
size = (sizeof(ccu_ncaiu1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
ccu_module_table = ccu_ncaiu2;
|
||||
size = (sizeof(ccu_ncaiu2) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 4:
|
||||
ccu_module_table = ccu_ncaiu3;
|
||||
size = (sizeof(ccu_ncaiu3) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 5:
|
||||
ccu_module_table = ccu_dce0;
|
||||
size = (sizeof(ccu_dce0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 6:
|
||||
ccu_module_table = ccu_dce1;
|
||||
size = (sizeof(ccu_dce1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 7:
|
||||
ccu_module_table = ccu_dmi0;
|
||||
size = (sizeof(ccu_dmi0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 8:
|
||||
ccu_module_table = ccu_dmi1;
|
||||
size = (sizeof(ccu_dmi1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 9:
|
||||
ccu_module_table = ccu_noc_fw_l4_per;
|
||||
size = (sizeof(ccu_noc_fw_l4_per) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 10:
|
||||
ccu_module_table = ccu_noc_fw_l4_sys;
|
||||
size = (sizeof(ccu_noc_fw_l4_sys) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 11:
|
||||
ccu_module_table = ccu_noc_fw_lwsoc2fpga;
|
||||
size = (sizeof(ccu_noc_fw_lwsoc2fpga) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 12:
|
||||
ccu_module_table = ccu_noc_fw_soc2fpga;
|
||||
size = (sizeof(ccu_noc_fw_soc2fpga) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
case 13:
|
||||
ccu_module_table = ccu_noc_fw_tcu;
|
||||
size = (sizeof(ccu_noc_fw_tcu) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
VERBOSE("CCU node base addr 0x%x, name %s, size 0x%x and module table %p\n",
|
||||
base, ncore_ccu_modules[index].name, size, (uint32_t *)ccu_module_table);
|
||||
|
||||
/*
|
||||
* First element: offset
|
||||
* Second element: val
|
||||
* Third element: mask
|
||||
*/
|
||||
for (int i = 0; i < size; i++) {
|
||||
offset = ccu_module_table[i].offset;
|
||||
val = ccu_module_table[i].val;
|
||||
|
||||
/* Reads the masking bit value from the list */
|
||||
mask = ccu_module_table[i].mask;
|
||||
|
||||
if (mask != 0) {
|
||||
if (mask == 0xFFFFFFFF) {
|
||||
reg = base + offset;
|
||||
mmio_write_32((uintptr_t)reg, val);
|
||||
} else {
|
||||
/* Mask the value with the masking bits */
|
||||
set_mask = val & mask;
|
||||
reg = base + offset;
|
||||
|
||||
/* Clears and sets specific bits in the register */
|
||||
mmio_clrsetbits_32((uintptr_t)reg, mask, set_mask);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static coh_ss_id_t subsystem_id;
|
||||
void get_subsystem_id(void)
|
||||
|
|
@ -29,6 +510,7 @@ void get_subsystem_id(void)
|
|||
subsystem_id.num_directory = directory;
|
||||
subsystem_id.num_coh_agent = coh_agent;
|
||||
}
|
||||
|
||||
uint32_t directory_init(void)
|
||||
{
|
||||
uint32_t dir_sf_mtn, dir_sf_en;
|
||||
|
|
@ -42,7 +524,7 @@ uint32_t directory_init(void)
|
|||
/* Poll Active Bit */
|
||||
ret = poll_active_bit(dir);
|
||||
if (ret != 0) {
|
||||
ERROR("Timeout during active bit polling");
|
||||
ERROR("Timeout during active bit polling\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
/* Disable snoop filter, a bit per snoop filter */
|
||||
|
|
@ -51,6 +533,7 @@ uint32_t directory_init(void)
|
|||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t coherent_agent_intfc_init(void)
|
||||
{
|
||||
uint32_t dir, ca, ca_id, ca_type, ca_snoop_en;
|
||||
|
|
@ -65,11 +548,12 @@ uint32_t coherent_agent_intfc_init(void)
|
|||
ca_type = CACHING_AGENT_TYPE(ca_id);
|
||||
if (ca_type == ACE_W_DVM || ca_type == ACE_L_W_DVM)
|
||||
mmio_setbits_32(NCORE_CCU_CSR(NCORE_CSADSER0),
|
||||
BIT(ca));
|
||||
BIT(ca));
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t poll_active_bit(uint32_t dir)
|
||||
{
|
||||
uint32_t timeout = 80000;
|
||||
|
|
@ -81,6 +565,7 @@ uint32_t poll_active_bit(uint32_t dir)
|
|||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
void bypass_ocram_firewall(void)
|
||||
{
|
||||
mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
|
||||
|
|
@ -92,6 +577,7 @@ void bypass_ocram_firewall(void)
|
|||
mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
|
||||
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
|
||||
}
|
||||
|
||||
void ncore_enable_ocram_firewall(void)
|
||||
{
|
||||
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
|
||||
|
|
@ -103,6 +589,8 @@ void ncore_enable_ocram_firewall(void)
|
|||
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
|
||||
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
|
||||
}
|
||||
|
||||
#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
|
||||
uint32_t init_ncore_ccu(void)
|
||||
{
|
||||
uint32_t status;
|
||||
|
|
@ -112,6 +600,7 @@ uint32_t init_ncore_ccu(void)
|
|||
bypass_ocram_firewall();
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
|
||||
void setup_smmu_stream_id(void)
|
||||
{
|
||||
|
|
@ -130,7 +619,6 @@ void setup_smmu_stream_id(void)
|
|||
mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN0), TSN0);
|
||||
mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN1), TSN1);
|
||||
mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN2), TSN2);
|
||||
|
||||
/* Enabled Stream ctrl register for Agilex5 */
|
||||
mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_CTRL_REG_0_DMA0), ENABLE_STREAMID);
|
||||
mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_CTRL_REG_0_DMA1), ENABLE_STREAMID);
|
||||
|
|
|
|||
|
|
@ -9,192 +9,206 @@
|
|||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "socfpga_plat_def.h"
|
||||
|
||||
#ifndef CCU_ACTIVATE_COH_FPGA
|
||||
#define CCU_ACTIVATE_COH_FPGA 0
|
||||
#define CCU_ACTIVATE_COH_FPGA 0
|
||||
#endif
|
||||
// Address map for ccu init
|
||||
#define addr_CAIUIDR1 (0x1C000000)
|
||||
#define addr_GRBUNRRUCR (0x1c0ffff8)
|
||||
#define base_addr_NRS_CAIU0 (0x1c000000)
|
||||
#define base_addr_NRS_NCAIU0 (0x1c001000)
|
||||
#define base_addr_NRS_NCAIU1 (0x1c002000)
|
||||
#define base_addr_NRS_NCAIU2 (0x1c003000)
|
||||
#define base_addr_NRS_NCAIU3 (0x1c004000)
|
||||
#define base_addr_NRS_DCE0 (0x1c005000)
|
||||
#define base_addr_NRS_DCE1 (0x1c006000)
|
||||
//#define base_addr_NRS_DMI0 (0x1c007000)
|
||||
//#define base_addr_NRS_DMI1 (0x1c008000)
|
||||
//DMI
|
||||
#define ALT_CCU_CCU_DMI0_DMIUSMCTCR_ADDR 0x1C007300
|
||||
#define ALT_CCU_CCU_DMI1_DMIUSMCTCR_ADDR 0x1C008300
|
||||
//DSU
|
||||
#define ALT_CCU_DSU_CAIUAMIGR_ADDR 0x1C0003C0
|
||||
#define ALT_CCU_DSU_CAIUMIFSR_ADDR 0x1C0003C4
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR1_ADDR 0x1C000414
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR1_ADDR 0x1C000418
|
||||
#define ALT_CCU_DSU_CAIUGPRAR1_ADDR 0x1C000410
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR2_ADDR 0x1C000424
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR2_ADDR 0x1C000428
|
||||
#define ALT_CCU_DSU_CAIUGPRAR2_ADDR 0x1C000420
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR4_ADDR 0x1C000444
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR4_ADDR 0x1C000448
|
||||
#define ALT_CCU_DSU_CAIUGPRAR4_ADDR 0x1C000440
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR5_ADDR 0x1C000454
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR5_ADDR 0x1C000458
|
||||
#define ALT_CCU_DSU_CAIUGPRAR5_ADDR 0x1C000450
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR6_ADDR 0x1C000464
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR6_ADDR 0x1C000468
|
||||
#define ALT_CCU_DSU_CAIUGPRAR6_ADDR 0x1C000460
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR7_ADDR 0x1C000474
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR7_ADDR 0x1C000478
|
||||
#define ALT_CCU_DSU_CAIUGPRAR7_ADDR 0x1C000470
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR8_ADDR 0x1C000484
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR8_ADDR 0x1C000488
|
||||
#define ALT_CCU_DSU_CAIUGPRAR8_ADDR 0x1C000480
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR9_ADDR 0x1C000494
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR9_ADDR 0x1C000498
|
||||
#define ALT_CCU_DSU_CAIUGPRAR9_ADDR 0x1C000490
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR10_ADDR 0x1C0004A4
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR10_ADDR 0x1C0004A8
|
||||
#define ALT_CCU_DSU_CAIUGPRAR10_ADDR 0x1C0004A0
|
||||
//GIC
|
||||
#define ALT_CCU_GIC_M_XAIUAMIGR_ADDR 0x1C0023C0
|
||||
#define ALT_CCU_GIC_M_XAIUMIFSR_ADDR 0x1C0023C4
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBLR1_ADDR 0x1C002414
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBHR1_ADDR 0x1C002418
|
||||
#define ALT_CCU_GIC_M_XAIUGPRAR1_ADDR 0x1C002410
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBLR6_ADDR 0x1C002464
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBHR6_ADDR 0x1C002468
|
||||
#define ALT_CCU_GIC_M_XAIUGPRAR6_ADDR 0x1C002460
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBLR8_ADDR 0x1C002484
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBHR8_ADDR 0x1C002488
|
||||
#define ALT_CCU_GIC_M_XAIUGPRAR8_ADDR 0x1C002480
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBLR10_ADDR 0x1C0024A4
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBHR10_ADDR 0x1C0024A8
|
||||
#define ALT_CCU_GIC_M_XAIUGPRAR10_ADDR 0x1C0024A0
|
||||
//FPGA2SOC
|
||||
#define ALT_CCU_FPGA2SOC_XAIUAMIGR_ADDR 0x1C0013C0
|
||||
#define ALT_CCU_FPGA2SOC_XAIUMIFSR_ADDR 0x1C0013C4
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBLR1_ADDR 0x1C001414
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBHR1_ADDR 0x1C001418
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRAR1_ADDR 0x1C001410
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBLR6_ADDR 0x1C001464
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBHR6_ADDR 0x1C001468
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRAR6_ADDR 0x1C001460
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBLR8_ADDR 0x1C001484
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBHR8_ADDR 0x1C001488
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRAR8_ADDR 0x1C001480
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBLR10_ADDR 0x1C0014A4
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBHR10_ADDR 0x1C0014A8
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRAR10_ADDR 0x1C0014A0
|
||||
//TCU
|
||||
#define ALT_CCU_TCU_BASE 0x1C003000
|
||||
#define ALT_CCU_TCU_XAIUAMIGR_ADDR ALT_CCU_TCU_BASE + 0x03C0
|
||||
#define ALT_CCU_TCU_XAIUMIFSR_ADDR ALT_CCU_TCU_BASE + 0x03C4
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR0_ADDR ALT_CCU_TCU_BASE + 0x0404
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR0_ADDR ALT_CCU_TCU_BASE + 0x0408
|
||||
#define ALT_CCU_TCU_XAIUGPRAR0_ADDR ALT_CCU_TCU_BASE + 0x0400
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR1_ADDR ALT_CCU_TCU_BASE + 0x0414
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR1_ADDR ALT_CCU_TCU_BASE + 0x0418
|
||||
#define ALT_CCU_TCU_XAIUGPRAR1_ADDR ALT_CCU_TCU_BASE + 0x0410
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR2_ADDR ALT_CCU_TCU_BASE + 0x0424
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR2_ADDR ALT_CCU_TCU_BASE + 0x0428
|
||||
#define ALT_CCU_TCU_XAIUGPRAR2_ADDR ALT_CCU_TCU_BASE + 0x0420
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR6_ADDR 0x1C003464
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR6_ADDR 0x1C003468
|
||||
#define ALT_CCU_TCU_XAIUGPRAR6_ADDR 0x1C003460
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR8_ADDR 0x1C003484
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR8_ADDR 0x1C003488
|
||||
#define ALT_CCU_TCU_XAIUGPRAR8_ADDR 0x1C003480
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR10_ADDR 0x1C0034A4
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR10_ADDR 0x1C0034A8
|
||||
#define ALT_CCU_TCU_XAIUGPRAR10_ADDR 0x1C0034A0
|
||||
//IOM
|
||||
#define ALT_CCU_CCU_IOM_XAIUAMIGR_ADDR 0x1C0043C0
|
||||
#define ALT_CCU_CCU_IOM_XAIUMIFSR_ADDR 0x1C0013C4
|
||||
#define ALT_CCU_IOM_XAIUGPRBLR1_ADDR 0x1C001414
|
||||
#define ALT_CCU_IOM_XAIUGPRBHR1_ADDR 0x1C001418
|
||||
#define ALT_CCU_IOM_XAIUGPRAR1_ADDR 0x1C001410
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBLR6_ADDR 0x1C001464
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBHR6_ADDR 0x1C001468
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRAR6_ADDR 0x1C001460
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBLR8_ADDR 0x1C001484
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBHR8_ADDR 0x1C001488
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRAR8_ADDR 0x1C001480
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBLR10_ADDR 0x1C0014A4
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBHR10_ADDR 0x1C0014A8
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRAR10_ADDR 0x1C0014A0
|
||||
//DCE
|
||||
#define ALT_CCU_DCE0_DCEUAMIGR_ADDR 0x1C0053C0
|
||||
#define ALT_CCU_DCE0_DCEUMIFSR_ADDR 0x1C0053C4
|
||||
#define ALT_CCU_DCE0_DCEUGPRBLR6_ADDR 0x1C005464
|
||||
#define ALT_CCU_DCE0_DCEUGPRBHR6_ADDR 0x1C005468
|
||||
#define ALT_CCU_DCE0_DCEUGPRAR6_ADDR 0x1C005460
|
||||
#define ALT_CCU_DCE0_DCEUGPRBLR8_ADDR 0x1C005484
|
||||
#define ALT_CCU_DCE0_DCEUGPRBHR8_ADDR 0x1C005488
|
||||
#define ALT_CCU_DCE0_DCEUGPRAR8_ADDR 0x1C005480
|
||||
#define ALT_CCU_DCE0_DCEUGPRBLR10_ADDR 0x1C0054A4
|
||||
#define ALT_CCU_DCE0_DCEUGPRBHR10_ADDR 0x1C0054A8
|
||||
#define ALT_CCU_DCE0_DCEUGPRAR10_ADDR 0x1C0054A0
|
||||
#define ALT_CCU_DCE1_DCEUAMIGR_ADDR 0x1C0063C0
|
||||
#define ALT_CCU_DCE1_DCEUMIFSR_ADDR 0x1C0063C4
|
||||
#define ALT_CCU_DCE1_DCEUGPRBLR6_ADDR 0x1C006464
|
||||
#define ALT_CCU_DCE1_DCEUGPRBHR6_ADDR 0x1C006468
|
||||
#define ALT_CCU_DCE1_DCEUGPRAR6_ADDR 0x1C006460
|
||||
#define ALT_CCU_DCE1_DCEUGPRBLR8_ADDR 0x1C006484
|
||||
#define ALT_CCU_DCE1_DCEUGPRBHR8_ADDR 0x1C006488
|
||||
#define ALT_CCU_DCE1_DCEUGPRAR8_ADDR 0x1C006480
|
||||
#define ALT_CCU_DCE1_DCEUGPRBLR10_ADDR 0x1C0064A4
|
||||
#define ALT_CCU_DCE1_DCEUGPRBHR10_ADDR 0x1C0064A8
|
||||
#define ALT_CCU_DCE1_DCEUGPRAR10_ADDR 0x1C0064A0
|
||||
#define offset_NRS_GPRAR0 (0x400)
|
||||
#define offset_NRS_GPRBLR0 (0x404)
|
||||
#define offset_NRS_GPRBHR0 (0x408)
|
||||
#define offset_NRS_GPRAR1 (0x410)
|
||||
#define offset_NRS_GPRBLR1 (0x414)
|
||||
#define offset_NRS_GPRBHR1 (0x418)
|
||||
#define offset_NRS_GPRAR2 (0x420)
|
||||
#define offset_NRS_GPRBLR2 (0x424)
|
||||
#define offset_NRS_GPRBHR2 (0x428)
|
||||
#define offset_NRS_GPRAR3 (0x430)
|
||||
#define offset_NRS_GPRBLR3 (0x434)
|
||||
#define offset_NRS_GPRBHR3 (0x438)
|
||||
#define offset_NRS_GPRAR4 (0x440)
|
||||
#define offset_NRS_GPRBLR4 (0x444)
|
||||
#define offset_NRS_GPRBHR4 (0x448)
|
||||
#define offset_NRS_GPRAR5 (0x450)
|
||||
#define offset_NRS_GPRBLR5 (0x454)
|
||||
#define offset_NRS_GPRBHR5 (0x458)
|
||||
#define offset_NRS_GPRAR6 (0x460)
|
||||
#define offset_NRS_GPRBLR6 (0x464)
|
||||
#define offset_NRS_GPRBHR6 (0x468)
|
||||
#define offset_NRS_GPRAR7 (0x470)
|
||||
#define offset_NRS_GPRBLR7 (0x474)
|
||||
#define offset_NRS_GPRBHR7 (0x478)
|
||||
#define offset_NRS_GPRAR8 (0x480)
|
||||
#define offset_NRS_GPRBLR8 (0x484)
|
||||
#define offset_NRS_GPRBHR8 (0x488)
|
||||
#define offset_NRS_GPRAR9 (0x490)
|
||||
#define offset_NRS_GPRBLR9 (0x494)
|
||||
#define offset_NRS_GPRBHR9 (0x498)
|
||||
#define offset_NRS_GPRAR10 (0x4a0)
|
||||
#define offset_NRS_GPRBLR10 (0x4a4)
|
||||
#define offset_NRS_GPRBHR10 (0x4a8)
|
||||
#define offset_NRS_AMIGR (0x3c0)
|
||||
#define offset_NRS_MIFSR (0x3c4)
|
||||
#define offset_NRS_DMIUSMCTCR (0x300)
|
||||
#define base_addr_DII0_PSSPERIPHS (0x10000)
|
||||
#define base_addr_DII0_LWHPS2FPGA (0x20000)
|
||||
#define base_addr_DII0_HPS2FPGA_1G (0x40000)
|
||||
#define base_addr_DII0_HPS2FPGA_15G (0x400000)
|
||||
#define base_addr_DII0_HPS2FPGA_240G (0x4000000)
|
||||
#define base_addr_DII1_MPFEREGS (0x18000)
|
||||
#define base_addr_DII2_GICREGS (0x1D000)
|
||||
#define base_addr_DII3_OCRAM (0x0)
|
||||
#define base_addr_BHR (0x0)
|
||||
#define base_addr_DMI_SDRAM_2G (0x80000)
|
||||
#define base_addr_DMI_SDRAM_30G (0x800000)
|
||||
#define base_addr_DMI_SDRAM_480G (0x8000000)
|
||||
|
||||
/* Macros */
|
||||
#define CCU_OFFSET_VAL_MASK 3U
|
||||
#define CCU_WORD_BYTE 4U
|
||||
|
||||
// Address Map for CCU Init
|
||||
#define addr_CAIUIDR1 SOCFPGA_CCU_NOC_REG_BASE + 0x00000
|
||||
#define addr_GRBUNRRUCR SOCFPGA_CCU_NOC_REG_BASE + 0xFFFF8
|
||||
#define base_addr_NRS_CAIU0 SOCFPGA_CCU_NOC_REG_BASE + 0x00000
|
||||
#define base_addr_NRS_NCAIU0 SOCFPGA_CCU_NOC_REG_BASE + 0x01000
|
||||
#define base_addr_NRS_NCAIU1 SOCFPGA_CCU_NOC_REG_BASE + 0x02000
|
||||
#define base_addr_NRS_NCAIU2 SOCFPGA_CCU_NOC_REG_BASE + 0x03000
|
||||
#define base_addr_NRS_NCAIU3 SOCFPGA_CCU_NOC_REG_BASE + 0x04000
|
||||
#define base_addr_NRS_DCE0 SOCFPGA_CCU_NOC_REG_BASE + 0x05000
|
||||
#define base_addr_NRS_DCE1 SOCFPGA_CCU_NOC_REG_BASE + 0x06000
|
||||
//#define base_addr_NRS_DMI0 SOCFPGA_CCU_NOC_REG_BASE + 0x07000
|
||||
//#define base_addr_NRS_DMI1 SOCFPGA_CCU_NOC_REG_BASE + 0x08000
|
||||
|
||||
/* DMI */
|
||||
#define ALT_CCU_CCU_DMI0_DMIUSMCTCR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x7300
|
||||
#define ALT_CCU_CCU_DMI1_DMIUSMCTCR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x8300
|
||||
|
||||
/* DSU */
|
||||
#define ALT_CCU_DSU_CAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3C0
|
||||
#define ALT_CCU_DSU_CAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3C4
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x414
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x418
|
||||
#define ALT_CCU_DSU_CAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x410
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x424
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x428
|
||||
#define ALT_CCU_DSU_CAIUGPRAR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x420
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x444
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x448
|
||||
#define ALT_CCU_DSU_CAIUGPRAR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x440
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x454
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x458
|
||||
#define ALT_CCU_DSU_CAIUGPRAR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x450
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x464
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x468
|
||||
#define ALT_CCU_DSU_CAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x460
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x474
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x478
|
||||
#define ALT_CCU_DSU_CAIUGPRAR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x470
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x484
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x488
|
||||
#define ALT_CCU_DSU_CAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x480
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x494
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x498
|
||||
#define ALT_CCU_DSU_CAIUGPRAR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x490
|
||||
#define ALT_CCU_DSU_CAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A4
|
||||
#define ALT_CCU_DSU_CAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A8
|
||||
#define ALT_CCU_DSU_CAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A0
|
||||
|
||||
/* GIC */
|
||||
#define ALT_CCU_GIC_M_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x23C0
|
||||
#define ALT_CCU_GIC_M_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x23C4
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2414
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2418
|
||||
#define ALT_CCU_GIC_M_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2410
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2464
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2468
|
||||
#define ALT_CCU_GIC_M_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2460
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2484
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2488
|
||||
#define ALT_CCU_GIC_M_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2480
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A4
|
||||
#define ALT_CCU_GIC_M_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A8
|
||||
#define ALT_CCU_GIC_M_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A0
|
||||
|
||||
/* FPGA2SOC */
|
||||
#define ALT_CCU_FPGA2SOC_BASE SOCFPGA_CCU_NOC_REG_BASE + 0x1000
|
||||
#define ALT_CCU_FPGA2SOC_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C0
|
||||
#define ALT_CCU_FPGA2SOC_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C4
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1414
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1418
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1410
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1464
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1468
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1460
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1484
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1488
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1480
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A4
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A8
|
||||
#define ALT_CCU_FPGA2SOC_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A0
|
||||
|
||||
/* TCU */
|
||||
#define ALT_CCU_TCU_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x33C0
|
||||
#define ALT_CCU_TCU_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x33C4
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3404
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3408
|
||||
#define ALT_CCU_TCU_XAIUGPRAR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3400
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3414
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3418
|
||||
#define ALT_CCU_TCU_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3410
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3424
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3428
|
||||
#define ALT_CCU_TCU_XAIUGPRAR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3420
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3464
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3468
|
||||
#define ALT_CCU_TCU_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3460
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3484
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3488
|
||||
#define ALT_CCU_TCU_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3480
|
||||
#define ALT_CCU_TCU_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A4
|
||||
#define ALT_CCU_TCU_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A8
|
||||
#define ALT_CCU_TCU_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A0
|
||||
|
||||
/* IOM */
|
||||
#define ALT_CCU_CCU_IOM_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x43C0
|
||||
#define ALT_CCU_CCU_IOM_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C4
|
||||
#define ALT_CCU_IOM_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1414
|
||||
#define ALT_CCU_IOM_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1418
|
||||
#define ALT_CCU_IOM_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1410
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1464
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1468
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1460
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1484
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1488
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1480
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A4
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A8
|
||||
#define ALT_CCU_CCU_IOM_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A0
|
||||
|
||||
/* DCE */
|
||||
#define ALT_CCU_DCE0_DCEUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x53C0
|
||||
#define ALT_CCU_DCE0_DCEUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x53C4
|
||||
#define ALT_CCU_DCE0_DCEUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5464
|
||||
#define ALT_CCU_DCE0_DCEUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5468
|
||||
#define ALT_CCU_DCE0_DCEUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5460
|
||||
#define ALT_CCU_DCE0_DCEUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5484
|
||||
#define ALT_CCU_DCE0_DCEUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5488
|
||||
#define ALT_CCU_DCE0_DCEUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5480
|
||||
#define ALT_CCU_DCE0_DCEUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A4
|
||||
#define ALT_CCU_DCE0_DCEUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A8
|
||||
#define ALT_CCU_DCE0_DCEUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A0
|
||||
#define ALT_CCU_DCE1_DCEUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x63C0
|
||||
#define ALT_CCU_DCE1_DCEUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x63C4
|
||||
#define ALT_CCU_DCE1_DCEUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6464
|
||||
#define ALT_CCU_DCE1_DCEUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6468
|
||||
#define ALT_CCU_DCE1_DCEUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6460
|
||||
#define ALT_CCU_DCE1_DCEUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6484
|
||||
#define ALT_CCU_DCE1_DCEUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6488
|
||||
#define ALT_CCU_DCE1_DCEUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6480
|
||||
#define ALT_CCU_DCE1_DCEUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A4
|
||||
#define ALT_CCU_DCE1_DCEUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A8
|
||||
#define ALT_CCU_DCE1_DCEUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A0
|
||||
#define offset_NRS_GPRAR0 0x400
|
||||
#define offset_NRS_GPRBLR0 0x404
|
||||
#define offset_NRS_GPRBHR0 0x408
|
||||
#define offset_NRS_GPRAR1 0x410
|
||||
#define offset_NRS_GPRBLR1 0x414
|
||||
#define offset_NRS_GPRBHR1 0x418
|
||||
#define offset_NRS_GPRAR2 0x420
|
||||
#define offset_NRS_GPRBLR2 0x424
|
||||
#define offset_NRS_GPRBHR2 0x428
|
||||
#define offset_NRS_GPRAR3 0x430
|
||||
#define offset_NRS_GPRBLR3 0x434
|
||||
#define offset_NRS_GPRBHR3 0x438
|
||||
#define offset_NRS_GPRAR4 0x440
|
||||
#define offset_NRS_GPRBLR4 0x444
|
||||
#define offset_NRS_GPRBHR4 0x448
|
||||
#define offset_NRS_GPRAR5 0x450
|
||||
#define offset_NRS_GPRBLR5 0x454
|
||||
#define offset_NRS_GPRBHR5 0x458
|
||||
#define offset_NRS_GPRAR6 0x460
|
||||
#define offset_NRS_GPRBLR6 0x464
|
||||
#define offset_NRS_GPRBHR6 0x468
|
||||
#define offset_NRS_GPRAR7 0x470
|
||||
#define offset_NRS_GPRBLR7 0x474
|
||||
#define offset_NRS_GPRBHR7 0x478
|
||||
#define offset_NRS_GPRAR8 0x480
|
||||
#define offset_NRS_GPRBLR8 0x484
|
||||
#define offset_NRS_GPRBHR8 0x488
|
||||
#define offset_NRS_GPRAR9 0x490
|
||||
#define offset_NRS_GPRBLR9 0x494
|
||||
#define offset_NRS_GPRBHR9 0x498
|
||||
#define offset_NRS_GPRAR10 0x4A0
|
||||
#define offset_NRS_GPRBLR10 0x4A4
|
||||
#define offset_NRS_GPRBHR10 0x4A8
|
||||
#define offset_NRS_AMIGR 0x3C0
|
||||
#define offset_NRS_MIFSR 0x3C4
|
||||
#define offset_NRS_DMIUSMCTCR 0x300
|
||||
#define base_addr_DII0_PSSPERIPHS 0x10000
|
||||
#define base_addr_DII0_LWHPS2FPGA 0x20000
|
||||
#define base_addr_DII0_HPS2FPGA_1G 0x40000
|
||||
#define base_addr_DII0_HPS2FPGA_15G 0x400000
|
||||
#define base_addr_DII0_HPS2FPGA_240G 0x4000000
|
||||
#define base_addr_DII1_MPFEREGS 0x18000
|
||||
#define base_addr_DII2_GICREGS 0x1D000
|
||||
#define base_addr_DII3_OCRAM 0x0
|
||||
#define base_addr_BHR 0x0
|
||||
#define base_addr_DMI_SDRAM_2G 0x80000
|
||||
#define base_addr_DMI_SDRAM_30G 0x800000
|
||||
#define base_addr_DMI_SDRAM_480G 0x8000000
|
||||
// ((0x0<<9) | (0xf<<20) | (0x1<<30) | (0x1<<31))
|
||||
#define wr_DII0_PSSPERIPHS 0xC0F00000
|
||||
// ((0x0<<9) | (0x11<<20) | (0x1<<30) | (0x1<<31))
|
||||
|
|
@ -228,54 +242,46 @@
|
|||
// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x17<<20) | (0x0<<30) | (0x1<<31))
|
||||
#define wr_DMI_SDRAM_30G 0x81700006
|
||||
// ((0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31))
|
||||
#define wr_DMI_SDRAM_240G_ORDERED 0x81a00000
|
||||
#define wr_DMI_SDRAM_240G_ORDERED 0x81A00000
|
||||
// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31))
|
||||
#define wr_DMI_SDRAM_240G 0x81a00006
|
||||
#define wr_DMI_SDRAM_240G 0x81A00006
|
||||
// ((0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31))
|
||||
#define wr_DMI_SDRAM_480G_ORDERED 0x81b00000
|
||||
#define wr_DMI_SDRAM_480G_ORDERED 0x81B00000
|
||||
// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31))
|
||||
#define wr_DMI_SDRAM_480G 0x81b00006
|
||||
#define wr_DMI_SDRAM_480G 0x81B00006
|
||||
|
||||
typedef enum CCU_REGION_SECURITY_e {
|
||||
//
|
||||
// Allow secure accesses only.
|
||||
//
|
||||
/* Allow secure accesses only. */
|
||||
CCU_REGION_SECURITY_SECURE_ONLY,
|
||||
//
|
||||
// Allow non-secure accesses only.
|
||||
//
|
||||
|
||||
/* Allow non-secure accesses only. */
|
||||
CCU_REGION_SECURITY_NON_SECURE_ONLY,
|
||||
//
|
||||
// Allow accesses of any security state.
|
||||
//
|
||||
|
||||
/* Allow accesses of any security state. */
|
||||
CCU_REGION_SECURITY_DONT_CARE
|
||||
} CCU_REGION_SECURITY_t;
|
||||
|
||||
typedef enum CCU_REGION_PRIVILEGE_e {
|
||||
//
|
||||
// Allow privileged accesses only.
|
||||
//
|
||||
/* Allow privileged accesses only. */
|
||||
CCU_REGION_PRIVILEGE_PRIVILEGED_ONLY,
|
||||
//
|
||||
// Allow unprivileged accesses only.
|
||||
//
|
||||
/* Allow unprivileged accesses only. */
|
||||
CCU_REGION_PRIVILEGE_NON_PRIVILEGED_ONLY,
|
||||
//
|
||||
// Allow accesses of any privilege.
|
||||
//
|
||||
/* Allow accesses of any privilege. */
|
||||
CCU_REGION_PRIVILEGE_DONT_CARE
|
||||
} CCU_REGION_PRIVILEGE_t;
|
||||
//
|
||||
// Initializes the CCU by enabling all regions except RAM 1 - 5.
|
||||
// This is needed because of an RTL change around 2016.02.24.
|
||||
//
|
||||
// Runtime measurement:
|
||||
// - arm : 14,830,000 ps (2016.05.31; sanity/printf_aarch32)
|
||||
// - aarch64 : 14,837,500 ps (2016.05.31; sanity/printf)
|
||||
//
|
||||
// Runtime history:
|
||||
// - arm : 20,916,668 ps (2016.05.30; sanity/printf_aarch32)
|
||||
// - aarch64 : 20,924,168 ps (2016.05.30; sanity/printf)
|
||||
//
|
||||
|
||||
/*
|
||||
* Initializes the CCU by enabling all regions except RAM 1 - 5.
|
||||
* This is needed because of an RTL change around 2016.02.24.
|
||||
*
|
||||
* Runtime measurement:
|
||||
* - arm : 14,830,000 ps (2016.05.31; sanity/printf_aarch32)
|
||||
* - aarch64 : 14,837,500 ps (2016.05.31; sanity/printf)
|
||||
*
|
||||
* Runtime history:
|
||||
* - arm : 20,916,668 ps (2016.05.30; sanity/printf_aarch32)
|
||||
* - aarch64 : 20,924,168 ps (2016.05.30; sanity/printf)
|
||||
*/
|
||||
int ccu_hps_init(void);
|
||||
|
||||
typedef enum ccu_hps_ram_region_e {
|
||||
|
|
@ -287,19 +293,21 @@ typedef enum ccu_hps_ram_region_e {
|
|||
ccu_hps_ram_region_ramspace5 = 5,
|
||||
} ccu_hps_ram_region_t;
|
||||
|
||||
// Disables a RAM (OCRAM) region with the given ID.
|
||||
/* Disables a RAM (OCRAM) region with the given ID. */
|
||||
int ccu_hps_ram_region_disable(int id);
|
||||
|
||||
// Enables a RAM (OCRAM) region with the given ID.
|
||||
/* Enables a RAM (OCRAM) region with the given ID. */
|
||||
int ccu_hps_ram_region_enable(int id);
|
||||
|
||||
// Attempts to remap a RAM (OCRAM) region with the given ID to span the given
|
||||
// start and end address. It also assigns the security and privilege policy.
|
||||
// Regions must be a power-of-two size with a minimum size of 64B.
|
||||
/*
|
||||
* Attempts to remap a RAM (OCRAM) region with the given ID to span the given
|
||||
* start and end address. It also assigns the security and privilege policy.
|
||||
* Regions must be a power-of-two size with a minimum size of 64B.
|
||||
*/
|
||||
int ccu_hps_ram_region_remap(int id, uintptr_t start, uintptr_t end,
|
||||
CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
|
||||
CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
|
||||
|
||||
// Verifies that all enabled RAM (OCRAM) regions does not overlap.
|
||||
/* Verifies that all enabled RAM (OCRAM) regions does not overlap. */
|
||||
int ccu_hps_ram_validate(void);
|
||||
|
||||
typedef enum ccu_hps_mem_region_e {
|
||||
|
|
@ -312,19 +320,21 @@ typedef enum ccu_hps_mem_region_e {
|
|||
ccu_hps_mem_region_memspace1e = 6,
|
||||
} ccu_hps_mem_region_t;
|
||||
|
||||
// Disables mem0 (DDR) region with the given ID.
|
||||
/* Disables mem0 (DDR) region with the given ID. */
|
||||
int ccu_hps_mem0_region_disable(int id);
|
||||
|
||||
// Enables mem0 (DDR) region with the given ID.
|
||||
/* Enables mem0 (DDR) region with the given ID. */
|
||||
int ccu_hps_mem0_region_enable(int id);
|
||||
|
||||
// Attempts to remap mem0 (DDR) region with the given ID to span the given
|
||||
// start and end address. It also assigns the security nad privlege policy.
|
||||
// Regions must be a power-of-two in size with a minimum size of 64B.
|
||||
/*
|
||||
* Attempts to remap mem0 (DDR) region with the given ID to span the given
|
||||
* start and end address. It also assigns the security nad privlege policy.
|
||||
* Regions must be a power-of-two in size with a minimum size of 64B.
|
||||
*/
|
||||
int ccu_hps_mem0_region_remap(int id, uintptr_t start, uintptr_t end,
|
||||
CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
|
||||
CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
|
||||
|
||||
// Verifies that all enabled mem0 (DDR) regions does not overlap.
|
||||
/* Verifies that all enabled mem0 (DDR) regions does not overlap. */
|
||||
int ccu_hps_mem0_validate(void);
|
||||
|
||||
typedef enum ccu_hps_ios_region_e {
|
||||
|
|
@ -342,14 +352,23 @@ typedef enum ccu_hps_ios_region_e {
|
|||
ccu_hps_ios_region_iospace2c = 11,
|
||||
} ccu_hps_ios_region_t;
|
||||
|
||||
// Disables the IOS (IO Slave) region with the given ID.
|
||||
/* Disables the IOS (IO Slave) region with the given ID. */
|
||||
int ccu_hps_ios_region_disable(int id);
|
||||
|
||||
// Enables the IOS (IO Slave) region with the given ID.
|
||||
/* Enables the IOS (IO Slave) region with the given ID. */
|
||||
int ccu_hps_ios_region_enable(int id);
|
||||
|
||||
typedef struct ncore_ccu_reg {
|
||||
char name[50];
|
||||
uint32_t base;
|
||||
uint32_t size;
|
||||
} ncore_ccu_reg_t;
|
||||
|
||||
#define NCORE_CCU_OFFSET 0xf7000000
|
||||
typedef struct ncore_ccu {
|
||||
uint32_t offset;
|
||||
uint32_t val;
|
||||
uint32_t mask;
|
||||
} ncore_ccu_t;
|
||||
|
||||
/* Coherent Sub-System Address Map */
|
||||
#define NCORE_CAIU_OFFSET 0x00000
|
||||
|
|
@ -358,43 +377,49 @@ int ccu_hps_ios_region_enable(int id);
|
|||
#define NCORE_NCBU_SIZE 0x01000
|
||||
#define NCORE_DIRU_OFFSET 0x80000
|
||||
#define NCORE_DIRU_SIZE 0x01000
|
||||
#define NCORE_CMIU_OFFSET 0xc0000
|
||||
#define NCORE_CMIU_OFFSET 0xC0000
|
||||
#define NCORE_CMIU_SIZE 0x01000
|
||||
#define NCORE_CSR_OFFSET 0xff000
|
||||
#define NCORE_CSR_OFFSET 0xFF000
|
||||
#define NCORE_CSADSERO 0x00040
|
||||
#define NCORE_CSUIDR 0x00ff8
|
||||
#define NCORE_CSIDR 0x00ffc
|
||||
#define NCORE_CSUIDR 0x00FF8
|
||||
#define NCORE_CSIDR 0x00FFC
|
||||
|
||||
/* Directory Unit Register Map */
|
||||
#define NCORE_DIRUSFER 0x00010
|
||||
#define NCORE_DIRUMRHER 0x00070
|
||||
#define NCORE_DIRUSFMCR 0x00080
|
||||
#define NCORE_DIRUSFMAR 0x00084
|
||||
|
||||
/* Coherent Agent Interface Unit Register Map */
|
||||
#define NCORE_CAIUIDR 0x00ffc
|
||||
#define NCORE_CAIUIDR 0x00FFC
|
||||
|
||||
/* Snoop Enable Register */
|
||||
#define NCORE_DIRUCASER0 0x00040
|
||||
#define NCORE_DIRUCASER1 0x00044
|
||||
#define NCORE_DIRUCASER2 0x00048
|
||||
#define NCORE_DIRUCASER3 0x0004c
|
||||
#define NCORE_DIRUCASER3 0x0004C
|
||||
#define NCORE_CSADSER0 0x00040
|
||||
#define NCORE_CSADSER1 0x00044
|
||||
#define NCORE_CSADSER2 0x00048
|
||||
#define NCORE_CSADSER3 0x0004c
|
||||
#define NCORE_CSADSER3 0x0004C
|
||||
|
||||
/* Protocols Definition */
|
||||
#define ACE_W_DVM 0
|
||||
#define ACE_L_W_DVM 1
|
||||
#define ACE_WO_DVM 2
|
||||
#define ACE_L_WO_DVM 3
|
||||
/* Bypass OC Ram Firewall */
|
||||
|
||||
/* Bypass OCRAM Firewall */
|
||||
#define NCORE_FW_OCRAM_BLK_BASE 0x100200
|
||||
#define NCORE_FW_OCRAM_BLK_CGF1 0x04
|
||||
#define NCORE_FW_OCRAM_BLK_CGF2 0x08
|
||||
#define NCORE_FW_OCRAM_BLK_CGF3 0x0c
|
||||
#define NCORE_FW_OCRAM_BLK_CGF3 0x0C
|
||||
#define NCORE_FW_OCRAM_BLK_CGF4 0x10
|
||||
#define OCRAM_PRIVILEGED_MASK BIT(29)
|
||||
#define OCRAM_SECURE_MASK BIT(30)
|
||||
|
||||
/* Macros */
|
||||
#define NCORE_CCU_REG(base) (NCORE_CCU_OFFSET + (base))
|
||||
#define NCORE_CCU_REG(base) (SOCFPGA_CCU_NOC_REG_BASE + (base))
|
||||
#define NCORE_CCU_CSR(reg) (NCORE_CCU_REG(NCORE_CSR_OFFSET)\
|
||||
+ (reg))
|
||||
#define NCORE_CCU_DIR(reg) (NCORE_CCU_REG(NCORE_DIRU_OFFSET)\
|
||||
|
|
@ -407,14 +432,14 @@ int ccu_hps_ios_region_enable(int id);
|
|||
+ NCORE_CAIU_SIZE * (x))
|
||||
#define COH_CPU0_BYPASS_REG(reg) (NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\
|
||||
+ (reg))
|
||||
#define CSUIDR_NUM_CMI(x) (((x) & 0x3f000000) >> 24)
|
||||
#define CSUIDR_NUM_DIR(x) (((x) & 0x003f0000) >> 16)
|
||||
#define CSUIDR_NUM_NCB(x) (((x) & 0x00003f00) >> 8)
|
||||
#define CSUIDR_NUM_CAI(x) (((x) & 0x0000007f) >> 0)
|
||||
#define CSIDR_NUM_SF(x) (((x) & 0x007c0000) >> 18)
|
||||
#define CSUIDR_NUM_CMI(x) (((x) & 0x3F000000) >> 24)
|
||||
#define CSUIDR_NUM_DIR(x) (((x) & 0x003F0000) >> 16)
|
||||
#define CSUIDR_NUM_NCB(x) (((x) & 0x00003F00) >> 8)
|
||||
#define CSUIDR_NUM_CAI(x) (((x) & 0x0000007F) >> 0)
|
||||
#define CSIDR_NUM_SF(x) (((x) & 0x007C0000) >> 18)
|
||||
#define SNOOP_FILTER_ID(x) (((x) << 16))
|
||||
#define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15)
|
||||
#define CACHING_AGENT_TYPE(x) (((x) & 0xf0000) >> 16)
|
||||
#define CACHING_AGENT_TYPE(x) (((x) & 0xF0000) >> 16)
|
||||
|
||||
typedef struct coh_ss_id {
|
||||
uint8_t num_coh_mem;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue