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feat(nxp-clk): enable the DDR clock
Enable the DDR clock by setting up its reset block, the associated partition and configuring the clock tree above the MC_CGM mux. Change-Id: Idfed24b3e74a189df87f9782886a91b906cd2022 Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This commit is contained in:
Ghennadi Procopciuc
parent
4a2ca71857
commit
8a4f840b1e
3 changed files with 130 additions and 5 deletions
drivers/nxp/clk/s32cc
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@ -14,6 +14,10 @@
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#define CGM0_BASE_ADDR (0x40030000UL)
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#define CGM1_BASE_ADDR (0x40034000UL)
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#define DDRPLL_BASE_ADDR (0x40044000UL)
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#define MC_ME_BASE_ADDR (0x40088000UL)
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#define MC_RGM_BASE_ADDR (0x40078000UL)
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#define RDC_BASE_ADDR (0x40080000UL)
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#define MC_CGM5_BASE_ADDR (0x40068000UL)
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/* FXOSC */
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#define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL)
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@ -4,15 +4,14 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <s32cc-clk-regs.h>
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#include <common/debug.h>
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#include <drivers/clk.h>
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#include <lib/mmio.h>
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#include <s32cc-clk-ids.h>
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#include <s32cc-clk-modules.h>
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#include <s32cc-clk-regs.h>
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#include <s32cc-clk-utils.h>
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#include <s32cc-mc-me.h>
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#define MAX_STACK_DEPTH (40U)
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@ -26,7 +25,11 @@ struct s32cc_clk_drv {
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uintptr_t armdfs_base;
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uintptr_t cgm0_base;
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uintptr_t cgm1_base;
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uintptr_t cgm5_base;
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uintptr_t ddrpll_base;
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uintptr_t mc_me;
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uintptr_t mc_rgm;
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uintptr_t rdc;
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};
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static int update_stack_depth(unsigned int *depth)
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@ -48,7 +51,11 @@ static struct s32cc_clk_drv *get_drv(void)
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.armdfs_base = ARM_DFS_BASE_ADDR,
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.cgm0_base = CGM0_BASE_ADDR,
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.cgm1_base = CGM1_BASE_ADDR,
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.cgm5_base = MC_CGM5_BASE_ADDR,
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.ddrpll_base = DDRPLL_BASE_ADDR,
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.mc_me = MC_ME_BASE_ADDR,
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.mc_rgm = MC_RGM_BASE_ADDR,
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.rdc = RDC_BASE_ADDR,
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};
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return &driver;
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@ -100,6 +107,9 @@ static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *d
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case S32CC_CGM1:
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*base = drv->cgm1_base;
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break;
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case S32CC_CGM5:
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*base = drv->cgm5_base;
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break;
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case S32CC_FIRC:
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break;
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case S32CC_SIRC:
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@ -598,6 +608,9 @@ static int enable_mux(struct s32cc_clk_obj *module,
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case S32CC_CGM0:
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ret = enable_cgm_mux(mux, drv);
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break;
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case S32CC_CGM5:
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ret = enable_cgm_mux(mux, drv);
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break;
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default:
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ERROR("Unknown mux parent type: %d\n", mux->module);
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ret = -EINVAL;
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@ -827,6 +840,86 @@ typedef int (*enable_clk_t)(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int depth);
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static int enable_part(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int depth)
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{
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const struct s32cc_part *part = s32cc_obj2part(module);
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uint32_t part_no = part->partition_id;
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if ((drv->mc_me == 0UL) || (drv->mc_rgm == 0UL) || (drv->rdc == 0UL)) {
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return -EINVAL;
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}
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return mc_me_enable_partition(drv->mc_me, drv->mc_rgm, drv->rdc, part_no);
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}
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static int enable_part_block(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int depth)
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{
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const struct s32cc_part_block *block = s32cc_obj2partblock(module);
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const struct s32cc_part *part = block->part;
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uint32_t part_no = part->partition_id;
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unsigned int ldepth = depth;
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uint32_t cofb;
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int ret;
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ret = update_stack_depth(&ldepth);
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if (ret != 0) {
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return ret;
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}
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if ((block->block >= s32cc_part_block0) &&
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(block->block <= s32cc_part_block15)) {
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cofb = (uint32_t)block->block - (uint32_t)s32cc_part_block0;
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mc_me_enable_part_cofb(drv->mc_me, part_no, cofb, block->status);
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} else {
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ERROR("Unknown partition block type: %d\n", block->block);
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return -EINVAL;
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}
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return 0;
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}
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static struct s32cc_clk_obj *
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get_part_block_parent(const struct s32cc_clk_obj *module)
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{
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const struct s32cc_part_block *block = s32cc_obj2partblock(module);
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return &block->part->desc;
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}
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static int enable_module_with_refcount(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int depth);
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static int enable_part_block_link(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int depth)
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{
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const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module);
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struct s32cc_part_block *block = link->block;
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unsigned int ldepth = depth;
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int ret;
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ret = update_stack_depth(&ldepth);
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if (ret != 0) {
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return ret;
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}
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/* Move the enablement algorithm to partition tree */
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return enable_module_with_refcount(&block->desc, drv, ldepth);
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}
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static struct s32cc_clk_obj *
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get_part_block_link_parent(const struct s32cc_clk_obj *module)
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{
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const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module);
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return link->parent;
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}
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static int no_enable(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int depth)
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@ -872,7 +965,7 @@ static int enable_module(struct s32cc_clk_obj *module,
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unsigned int depth)
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{
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struct s32cc_clk_obj *parent = get_module_parent(module);
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static const enable_clk_t enable_clbs[8] = {
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static const enable_clk_t enable_clbs[12] = {
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[s32cc_clk_t] = no_enable,
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[s32cc_osc_t] = enable_osc,
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[s32cc_pll_t] = enable_pll,
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@ -881,6 +974,9 @@ static int enable_module(struct s32cc_clk_obj *module,
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[s32cc_shared_clkmux_t] = enable_mux,
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[s32cc_dfs_t] = enable_dfs,
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[s32cc_dfs_div_t] = enable_dfs_div,
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[s32cc_part_t] = enable_part,
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[s32cc_part_block_t] = enable_part_block,
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[s32cc_part_block_link_t] = enable_part_block_link,
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};
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uint32_t index;
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int ret = 0;
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@ -1244,7 +1340,7 @@ typedef struct s32cc_clk_obj *(*get_parent_clb_t)(const struct s32cc_clk_obj *cl
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static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module)
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{
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static const get_parent_clb_t parents_clbs[8] = {
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static const get_parent_clb_t parents_clbs[12] = {
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[s32cc_clk_t] = get_clk_parent,
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[s32cc_osc_t] = get_no_parent,
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[s32cc_pll_t] = get_pll_parent,
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@ -1253,6 +1349,9 @@ static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *modul
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[s32cc_shared_clkmux_t] = get_mux_parent,
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[s32cc_dfs_t] = get_dfs_parent,
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[s32cc_dfs_div_t] = get_dfs_div_parent,
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[s32cc_part_t] = get_no_parent,
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[s32cc_part_block_t] = get_part_block_parent,
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[s32cc_part_block_link_t] = get_part_block_link_parent,
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};
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uint32_t index;
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@ -163,6 +163,23 @@ static int setup_ddr_pll(void)
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return ret;
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}
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static int enable_ddr_clk(void)
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{
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int ret;
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ret = clk_set_parent(S32CC_CLK_MC_CGM5_MUX0, S32CC_CLK_DDR_PLL_PHI0);
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if (ret != 0) {
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return ret;
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}
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ret = clk_enable(S32CC_CLK_DDR);
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if (ret != 0) {
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return ret;
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}
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return ret;
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}
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int s32cc_init_early_clks(void)
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{
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int ret;
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@ -204,5 +221,10 @@ int s32cc_init_early_clks(void)
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return ret;
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}
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ret = enable_ddr_clk();
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if (ret != 0) {
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return ret;
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}
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return ret;
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}
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