RTC clock configuration is done now in OPTEE.
Note: The RTC clock source can only be configured once.
TF-A, configuring the RTC clock source will have no effect in OPTEE.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I111ba96b27d0de0c45086ba8ef947dd2e6785672
Those functions are only used on MP1, they should not be in STM32 clock
core. Move them to MP13 driver (they are already in MP15 driver).
Redefine new clk_stm32_rcc_regs_*lock() functions in clock core. This
change avoid sparse warning:
drivers/st/clk/clk-stm32-core.c:46:6: warning: symbol
'stm32mp1_clk_rcc_regs_lock' was not declared. Should it be static?
drivers/st/clk/clk-stm32-core.c:51:6: warning: symbol
'stm32mp1_clk_rcc_regs_unlock' was not declared. Should it be static?
Change-Id: I9f255acaa843e41fc14267c1a8091f93bd029796
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Re-ordering structures to avoid gaps and minimize data.
Reduce type of gate_refcounts[], uint8_t is enough.
Re-ordering structures to avoid gaps and minimize data.
Use an unsigned char to define a clock ops type.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I6b793dc34abdd6ef013609fc0f122da5d1824a34
TF-A BL32 (SP_MIN) is not supported on STM32MP13. Only OP-TEE is used
as BL32. Remove the code under IMAGE_BL32 flag in STM32MP13 driver.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6cc9f230782c44129b205e66a44cdb4bcb5f95c3
If the oscillator is not present, the gating will fail.
Change-Id: If9119460a4bcd42053537f1975afe5fe1df05752
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
TF-A BL2 always boot at 650MHz using an algorithm to calculate PLL1
settings, without reading DT. Remove the corresponding nodes.
Change-Id: I0003337d8d37df7b2a70a84b5475f4278c4c4669
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
RCC bindings alignment with MP13 RCC bindings:
- merge of 'st,clksrc' and 'st,pkcs' nodes into 'st,clksrc'
- no ordering requirements on 'st,clksrc' node
- use DIV() macro for 'st,clkdiv' node
- no ordering requirements on 'st,clkdiv' node
- new pll binding
Change-Id: Id3ca30608dde2091145123512c42c6958a378d91
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Switching to higher CPU frequencies requires a dedicated chip version
(STM32MP1xxD or STM32MP1xxF), and increase CPU voltage. To avoid
re-configuring I2C and PMIC before and after applying clock tree,
always boot at 650MHz, which is the frequency for nominal voltage.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id05a3ee17e7dd57e2d64dc06f8f1e7f9cb21e110
Remove useless LSEDRV_MEDIUM_HIGH definition in clk-stm32mp13.c.
It's already defined in include/dt-bindings/clock/stm32mp13-clksrc.h.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ie3fa4711930f922fa0733ba7c76d72ec9639e9a5
The PLL clk_id does not start at 0, but it is in the enum listing all
clocks. To have a better display of the PLL number, start at PLL1,
by changing pll->clk_id in messages with pll->clk_id - _CK_PLL1 + 1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ic09195ae6fe5f8d3a87e69962425f7c826f3670b
If LSE oscillator is already ON, which is the case when returning from
low-power state or if we are on VBAT, it mustn't be reconfigured.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ie75f2b0b42aeb3d95e2266e1fca811a2f2b3e29f
LSI was too slow to provide enough random numbers (limited
to 6ms for 16 bytes production). Switch to CSI that allow
to get the RNG fifo ready in less than 50µs.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I76d1fe58e2f4d5416a96f48123ae36bd82d8a8ee
Remove the unused functions in stm32mp clk API:
- stm32mp_stgen_get_counter (change to static, no more exported)
- stm32mp_stgen_restore_counter
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ib6ca72723eac3e133f1ca0dee504ef344c72e0bf
Update function stm32mp_stgen_config() to support deactivated STGEN
when frequency is 0, for example on STOP2 exit for STM32MP25.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id371c4602a614bbfa0ecc7ce2d2e0ac5261e1d52
Add a function to restore the CPU generic timer rate from STGEN content.
After wake-up from LPLV-Stop2, STGEN content is not lost, but generic timer
has been reset.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I6f91dbd051f76383e9ff1d6bb86225d373dbf33a
Nothing in sunxi_bl31_setup.c uses any functionality provided by the
fdt_wrappers file, so remove its inclusion from the header list.
Change-Id: I47031a58add2f85e757e75d8578f4e8e21ef65ea
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c
Currently, if SGI is not registered by Linux and power down event from
firmware is received then it's not getting handled in TF-A and core power
down is not happening. Because of that subsystem restart or force power
down without Linux boot is not happening. So, handle power down event in
TF-A if Linux not registered SGI.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0c23792daba6ae47004ae99e232c77e17230bcfb
Currently, only Linux registering for getting idle callback during
subsystem restart or force power down. Because of that if Linux boot
hang or someone wants to do subsystem restart before Linux boot then
it's not working. So, register for idle callback in TF-A to get idle
callback during subsystem restart or force power down to do ARM
specific steps for proper power down of core.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: If7c01f79be6958678243be844bcfdc50d59b0fb8
This patch fixes fill_l1_tbl() function bug
for RME_GPT_MAX_BLOCK build option set to 0
disabling filling L1 tables with Contiguous
descriptors.
Change-Id: I3eedd6c1bb55b7c207bb3630d1ab2fda8f72eb17
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Today, the PM_IOCTL and PM_QUERY_DATA APIs are there to maintain
backward compatibility. Now, the usage of these APIs on the Linux
side and the firmware side is updated. Hence remove the deprecated
PM_IOCTL and PM_QUERY_DATA EEMI API from the TF-A to make TF-A pass
through.
Note: Only use the newer kernel to access the deprecated features in
this patch. Otherwise, the system may not function correctly.
Change-Id: I23effb7ff62e7f83563c2b422ea64a0289fd880f
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
MAP_DEVICE0 for internal (register) space access settings
flag MT_NS was changed to MT_SECURE to enable access
to the TSGEN register, otherwise it brings to MCR violation,
because access to the TSGEN register is locked and enabled
for secure only
Change-Id: Id2fe90d30342706c58064161360d8be6e0d5616b
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Since the CoT device tree is intended solely for BL2, remove the
nodes that are not handled by BL2.
Change-Id: I977eec902f16de59743e97d15148d63934b7b863
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Add an explicit entry for HW_CONFIG in the BL2 CoT file for the Juno
platform, as the HW_CONFIG node has been removed from the common CoT
file.
Change-Id: I8a1a22dd1023895cfc5730101fad20a80390ce17
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Remove the 'HW_CONFIG' reference from the BL1 CoT file, as BL1
does not play any role in loading the hw_config image. This
reference was incorrectly added to the BL1 CoT file.
Change-Id: I9c1d9abce65844eaa1f41ab4f98d3c258ab7a8d2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
The Makefile rule for the libwrappers object files places a dependency
on a timestamp file. This timestamp file is created by the recipe that
generates the libwrappers sources, and was presumably introduced to
indicate to Make that all of the source files are generated
simultaneously by that rule.
Instead, we can use a grouped target rule, which uses `&:` instead of
`:`. This communicates to Make that all of the targets listed are
generated at once.
To demonstrate, the following two Makefile rules differ in their
behaviour:
a.x b.x c.x: # targets may be updated independently
... # generate a.x, b.x and c.x
a.x b.x c.x &: # all targets are updated at once
... # generate a.x, b.x and c.x
While both recipes do generate all three files, only the second rule
communicates this fact to Make. As such, Make can reason that if one of
the files is up to date then all of them are, and avoid re-running the
rule for any generated file that it has not already run it for.
Change-Id: I10b49eb72b5276c7f9bd933900833b03a61cff2f
Signed-off-by: Chris Kay <chris.kay@arm.com>
The `romlib_generator.py` script may generate duplicate wrapper sources,
which is undesirable when using them to generate Makefile rules as Make
will warn about duplicated targets.
This change sorts the wrapper sources returned from this script, which
has the effect of also de-duplicating them.
Change-Id: I109607ef94f77113a48cc0d6e07877efd1971dbc
Signed-off-by: Chris Kay <chris.kay@arm.com>
Preprocessor definitions that are passed to armlink are currently not
correctly escaped, resulting in the shell trying to parse the
parentheses contained in some of the preprocessor definitions:
```
LD build/tegra/t210/release/bl31/bl31.elf
/bin/sh: 1: Syntax error: "(" unexpected
```
This change ensures that these preprocessor definitions are adequately
escaped for the shell.
Change-Id: I9d2c60fa60c0aa00770417a68f900e9fb84b4669
Signed-off-by: Chris Kay <chris.kay@arm.com>
This patch updates GPT library design documentation
with the changes introduced by patches which add
support for large GPT mappings and configuration of
memory size protected by bitlock.
Change-Id: I1f97fa8f003deb07a5f32b7237c1927581a788c8
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Add an `stdout-path' property into the `chosen' node of the Foundation
FVPs Devicetrees.
This gives a default console to the Linux kernel when "console=" is not
specified on the kernel command line, which is useful when booting with
U-Boot in UEFI for example.
Change-Id: I27d5f7f9416bd42b7401b1a57ae64bfee2524204
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
'cpu_partnumber' variable part of 'em_cpu_list' actually contains the
cpu midr value and not the actual part number. The part number is
extracted from midr value in 'non_arm_interconnect_errata' function.
So 'cpu_partnumber' is misleading and the actual value is midr, thus
rename it to 'cpu_midr'.
Change-Id: I4bfe71ce24542d508e2bcf39a1097724d14c4511
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
