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refactor(st-clock): remove BL32 support on STM32MP13
TF-A BL32 (SP_MIN) is not supported on STM32MP13. Only OP-TEE is used as BL32. Remove the code under IMAGE_BL32 flag in STM32MP13 driver. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I6cc9f230782c44129b205e66a44cdb4bcb5f95c3
This commit is contained in:
Yann Gautier
parent
f2aebab859
commit
698bba5e74
1 changed files with 1 additions and 115 deletions
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@ -186,65 +186,7 @@ enum stm32_clock {
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_MCE,
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_FMC_K,
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_QSPI_K,
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#if defined(IMAGE_BL32)
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_LTDC,
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_DMA1,
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_DMA2,
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_MDMA,
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_ETH1MAC,
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_USBH,
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_TIM2,
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_TIM3,
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_TIM4,
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_TIM5,
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_TIM6,
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_TIM7,
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_LPTIM1_K,
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_SPI2_K,
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_SPI3_K,
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_SPDIF_K,
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_TIM1,
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_TIM8,
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_SPI1_K,
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_SAI1_K,
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_SAI2_K,
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_DFSDM,
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_FDCAN_K,
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_TIM13,
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_TIM14,
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_TIM16,
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_TIM17,
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_SPI4_K,
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_SPI5_K,
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_I2C1_K,
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_I2C2_K,
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_ADFSDM,
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_LPTIM2_K,
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_LPTIM3_K,
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_LPTIM4_K,
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_LPTIM5_K,
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_VREF,
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_DTS,
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_PMBCTRL,
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_HDP,
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_STGENRO,
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_DCMIPP_K,
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_DMAMUX1,
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_DMAMUX2,
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_DMA3,
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_ADC1_K,
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_ADC2_K,
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_TSC,
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_AXIMC,
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_ETH1CK,
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_ETH1TX,
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_ETH1RX,
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_CRC1,
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_ETH2CK,
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_ETH2TX,
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_ETH2RX,
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_ETH2MAC,
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#endif
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CK_LAST
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};
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@ -2004,7 +1946,6 @@ static const struct clk_stm32 stm32mp13_clk[CK_LAST] = {
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STM32_GATE(_SDMMC2_K, SDMMC2_K, MUX(MUX_SDMMC2), 0, GATE_SDMMC2),
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STM32_GATE(_DBGCK, CK_DBG, _CKAXI, 0, GATE_DBGCK),
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/* TODO: CHECK CLOCK FOR BL2/BL32 AND IF ONLY FOR TEST OR NOT */
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STM32_GATE(_USART3_K, USART3_K, MUX(MUX_UART35), 0, GATE_USART3),
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STM32_GATE(_UART4_K, UART4_K, MUX(MUX_UART4), 0, GATE_UART4),
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STM32_GATE(_UART5_K, UART5_K, MUX(MUX_UART35), 0, GATE_UART5),
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@ -2018,61 +1959,6 @@ static const struct clk_stm32 stm32mp13_clk[CK_LAST] = {
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STM32_COMPOSITE(_MCO1_K, CK_MCO1, MUX(MUX_MCO1), 0, GATE_MCO1, DIV_MCO1),
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STM32_COMPOSITE(_MCO2_K, CK_MCO2, MUX(MUX_MCO2), 0, GATE_MCO2, DIV_MCO2),
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STM32_COMPOSITE(_TRACECK, CK_TRACE, _CKAXI, 0, GATE_TRACECK, DIV_TRACE),
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#if defined(IMAGE_BL32)
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STM32_GATE(_TIM2, TIM2_K, _CKTIMG1, 0, GATE_TIM2),
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STM32_GATE(_TIM3, TIM3_K, _CKTIMG1, 0, GATE_TIM3),
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STM32_GATE(_TIM4, TIM4_K, _CKTIMG1, 0, GATE_TIM4),
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STM32_GATE(_TIM5, TIM5_K, _CKTIMG1, 0, GATE_TIM5),
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STM32_GATE(_TIM6, TIM6_K, _CKTIMG1, 0, GATE_TIM6),
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STM32_GATE(_TIM7, TIM7_K, _CKTIMG1, 0, GATE_TIM7),
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STM32_GATE(_TIM13, TIM13_K, _CKTIMG3, 0, GATE_TIM13),
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STM32_GATE(_TIM14, TIM14_K, _CKTIMG3, 0, GATE_TIM14),
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STM32_GATE(_LPTIM1_K, LPTIM1_K, MUX(MUX_LPTIM1), 0, GATE_LPTIM1),
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STM32_GATE(_SPI2_K, SPI2_K, MUX(MUX_SPI23), 0, GATE_SPI2),
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STM32_GATE(_SPI3_K, SPI3_K, MUX(MUX_SPI23), 0, GATE_SPI3),
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STM32_GATE(_SPDIF_K, SPDIF_K, MUX(MUX_SPDIF), 0, GATE_SPDIF),
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STM32_GATE(_TIM1, TIM1_K, _CKTIMG2, 0, GATE_TIM1),
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STM32_GATE(_TIM8, TIM8_K, _CKTIMG2, 0, GATE_TIM8),
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STM32_GATE(_TIM16, TIM16_K, _CKTIMG3, 0, GATE_TIM16),
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STM32_GATE(_TIM17, TIM17_K, _CKTIMG3, 0, GATE_TIM17),
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STM32_GATE(_SPI1_K, SPI1_K, MUX(MUX_SPI1), 0, GATE_SPI1),
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STM32_GATE(_SPI4_K, SPI4_K, MUX(MUX_SPI4), 0, GATE_SPI4),
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STM32_GATE(_SPI5_K, SPI5_K, MUX(MUX_SPI5), 0, GATE_SPI5),
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STM32_GATE(_SAI1_K, SAI1_K, MUX(MUX_SAI1), 0, GATE_SAI1),
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STM32_GATE(_SAI2_K, SAI2_K, MUX(MUX_SAI2), 0, GATE_SAI2),
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STM32_GATE(_DFSDM, DFSDM_K, MUX(MUX_SAI1), 0, GATE_DFSDM),
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STM32_GATE(_FDCAN_K, FDCAN_K, MUX(MUX_FDCAN), 0, GATE_FDCAN),
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STM32_GATE(_USBH, USBH, _CKAXI, 0, GATE_USBH),
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STM32_GATE(_I2C1_K, I2C1_K, MUX(MUX_I2C12), 0, GATE_I2C1),
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STM32_GATE(_I2C2_K, I2C2_K, MUX(MUX_I2C12), 0, GATE_I2C2),
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STM32_GATE(_ADFSDM, ADFSDM_K, MUX(MUX_SAI1), 0, GATE_ADFSDM),
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STM32_GATE(_LPTIM2_K, LPTIM2_K, MUX(MUX_LPTIM2), 0, GATE_LPTIM2),
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STM32_GATE(_LPTIM3_K, LPTIM3_K, MUX(MUX_LPTIM3), 0, GATE_LPTIM3),
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STM32_GATE(_LPTIM4_K, LPTIM4_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM4),
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STM32_GATE(_LPTIM5_K, LPTIM5_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM5),
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STM32_GATE(_VREF, VREF, _PCLK3, 0, GATE_VREF),
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STM32_GATE(_DTS, TMPSENS, _PCLK3, 0, GATE_DTS),
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STM32_GATE(_PMBCTRL, PMBCTRL, _PCLK3, 0, GATE_HDP),
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STM32_GATE(_HDP, HDP, _PCLK3, 0, GATE_PMBCTRL),
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STM32_GATE(_STGENRO, STGENRO, _PCLK4, 0, GATE_DCMIPP),
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STM32_GATE(_DCMIPP_K, DCMIPP_K, MUX(MUX_DCMIPP), 0, GATE_DCMIPP),
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STM32_GATE(_DMAMUX1, DMAMUX1, _CKAXI, 0, GATE_DMAMUX1),
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STM32_GATE(_DMAMUX2, DMAMUX2, _CKAXI, 0, GATE_DMAMUX2),
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STM32_GATE(_DMA3, DMA3, _CKAXI, 0, GATE_DMAMUX2),
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STM32_GATE(_ADC1_K, ADC1_K, MUX(MUX_ADC1), 0, GATE_ADC1),
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STM32_GATE(_ADC2_K, ADC2_K, MUX(MUX_ADC2), 0, GATE_ADC2),
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STM32_GATE(_TSC, TSC, _CKAXI, 0, GATE_TSC),
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STM32_GATE(_AXIMC, AXIMC, _CKAXI, 0, GATE_AXIMC),
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STM32_GATE(_CRC1, CRC1, _CKAXI, 0, GATE_ETH1TX),
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STM32_GATE(_ETH1CK, ETH1CK_K, MUX(MUX_ETH1), 0, GATE_ETH1CK),
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STM32_GATE(_ETH1TX, ETH1TX, _CKAXI, 0, GATE_ETH1TX),
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STM32_GATE(_ETH1RX, ETH1RX, _CKAXI, 0, GATE_ETH1RX),
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STM32_GATE(_ETH2CK, ETH2CK_K, MUX(MUX_ETH2), 0, GATE_ETH2CK),
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STM32_GATE(_ETH2TX, ETH2TX, _CKAXI, 0, GATE_ETH2TX),
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STM32_GATE(_ETH2RX, ETH2RX, _CKAXI, 0, GATE_ETH2RX),
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STM32_GATE(_ETH2MAC, ETH2MAC, _CKAXI, 0, GATE_ETH2MAC),
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#endif
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};
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static struct stm32_pll_dt_cfg mp13_pll[_PLL_NB];
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