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https://github.com/ARM-software/arm-trusted-firmware.git
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feat(stm32mp1): always boot at 650MHz
Switching to higher CPU frequencies requires a dedicated chip version (STM32MP1xxD or STM32MP1xxF), and increase CPU voltage. To avoid re-configuring I2C and PMIC before and after applying clock tree, always boot at 650MHz, which is the frequency for nominal voltage. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Change-Id: Id05a3ee17e7dd57e2d64dc06f8f1e7f9cb21e110
This commit is contained in:
Yann Gautier
parent
6583da67d6
commit
f655922788
3 changed files with 280 additions and 19 deletions
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@ -1357,6 +1357,123 @@ static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx)
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return &pdata->pll[pll_idx];
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}
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/* Define characteristic for PLL1 : PLL_2000 */
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#define POST_DIVM_MIN 8000000U
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#define POST_DIVM_MAX 16000000U
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#define DIVM_MIN 0U
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#define DIVM_MAX 63U
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#define DIVN_MIN 24U
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#define DIVN_MAX 99U
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#define DIVP_MIN 0U
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#define DIVP_MAX 127U
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#define FRAC_MAX 8192U
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#define VCO_MIN 992000000U
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#define VCO_MAX 2000000000U
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static int clk_compute_pll1_settings(uint32_t freq_khz)
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{
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struct stm32_clk_priv *priv = clk_stm32_get_priv();
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struct stm32_pll_dt_cfg *pll1 = clk_stm32_pll_get_pdata(_PLL1);
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struct stm32_pll_dt_cfg *pll2 = clk_stm32_pll_get_pdata(_PLL2);
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unsigned long long best_diff = ULLONG_MAX;
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unsigned int divm;
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unsigned long input_freq = 0UL;
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uint32_t src = pll2->vco.src;
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/* PLL1 share the same clock source than PLL2 */
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switch (src) {
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case CLK_PLL12_HSI:
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input_freq = _clk_stm32_get_rate(priv, _CK_HSI);
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break;
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case CLK_PLL12_HSE:
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input_freq = _clk_stm32_get_rate(priv, _CK_HSE);
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break;
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default:
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break;
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}
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if (input_freq == 0UL) {
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panic();
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}
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/* Following parameters have always the same value */
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pll1->output.output[PLL_CFG_Q] = 0U;
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pll1->output.output[PLL_CFG_R] = 0U;
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for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) {
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unsigned long post_divm = input_freq / divm;
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unsigned int divp;
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if ((post_divm < POST_DIVM_MIN) || (post_divm > POST_DIVM_MAX)) {
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continue;
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}
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for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
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unsigned long long output_freq = freq_khz * 1000ULL;
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unsigned long long freq;
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unsigned long long divn;
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unsigned long long frac;
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unsigned int i;
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freq = output_freq * divm * (divp + 1U);
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divn = (freq / input_freq) - 1U;
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if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) {
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continue;
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}
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frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX);
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/* 2 loops to refine the fractional part */
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for (i = 2U; i != 0U; i--) {
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unsigned long long diff;
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unsigned long long vco;
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if (frac > FRAC_MAX) {
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break;
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}
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vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX);
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if ((vco < (VCO_MIN / 2U)) || (vco > (VCO_MAX / 2U))) {
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frac++;
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continue;
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}
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freq = vco / (divp + 1U);
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if (output_freq < freq) {
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diff = freq - output_freq;
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} else {
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diff = output_freq - freq;
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}
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if (diff < best_diff) {
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pll1->vco.src = src;
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pll1->vco.status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_PLLON;
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pll1->vco.div_mn[PLL_CFG_M] = divm - 1U;
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pll1->vco.div_mn[PLL_CFG_N] = (uint32_t)divn;
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pll1->vco.frac = (uint32_t)frac;
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pll1->output.output[PLL_CFG_P] = divp;
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if (diff == 0U) {
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return 0;
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}
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best_diff = diff;
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}
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frac++;
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}
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}
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}
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if (best_diff == ULLONG_MAX) {
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return -EINVAL;
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}
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return 0;
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}
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static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
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{
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uintptr_t pll_base = priv->base + pll->reg_pllxcr;
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@ -2244,7 +2361,8 @@ static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_pla
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{
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size_t i = 0U;
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for (i = _PLL1; i < pdata->npll; i++) {
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/* PLL1 is not configurable with device tree */
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for (i = _PLL2; i < pdata->npll; i++) {
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struct stm32_pll_dt_cfg *pll = &pdata->pll[i];
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char name[RCC_PLL_NAME_SIZE];
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int subnode = 0;
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@ -2306,6 +2424,21 @@ static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata)
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int stm32mp1_clk_init(void)
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{
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int ret;
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/* compute the PLL1 settings, not read in device tree */
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ret = clk_compute_pll1_settings(PLL1_NOMINAL_FREQ_IN_KHZ);
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if (ret != 0) {
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return ret;
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}
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ret = stm32mp1_init_clock_tree();
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if (ret != 0) {
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return ret;
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}
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clk_stm32_enable_critical_clocks();
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return 0;
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}
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@ -2320,16 +2453,6 @@ int stm32mp1_clk_probe(void)
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}
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ret = clk_stm32_init(&stm32mp13_clock_data, base);
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if (ret != 0) {
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return ret;
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}
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ret = stm32mp1_init_clock_tree();
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if (ret != 0) {
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return ret;
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}
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clk_stm32_enable_critical_clocks();
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return 0;
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return ret;
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}
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@ -537,7 +537,18 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
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};
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/* Define characteristic of PLL according type */
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#define DIVN_MIN 24
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#define POST_DIVM_MIN 8000000U
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#define POST_DIVM_MAX 16000000U
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#define DIVM_MIN 0U
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#define DIVM_MAX 63U
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#define DIVN_MIN 24U
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#define DIVN_MAX 99U
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#define DIVP_MIN 0U
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#define DIVP_MAX 127U
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#define FRAC_MAX 8192U
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#define VCO_MIN 800000000U
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#define VCO_MAX 1600000000U
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static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
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[PLL_800] = {
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.refclk_min = 4,
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@ -1813,6 +1824,116 @@ static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg,
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return ret;
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}
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static int clk_compute_pll1_settings(unsigned long input_freq,
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uint32_t freq_khz,
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uint32_t *pllcfg, uint32_t *fracv)
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{
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unsigned long long best_diff = ULLONG_MAX;
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unsigned int divm;
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/* Following parameters have always the same value */
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pllcfg[PLLCFG_Q] = 0U;
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pllcfg[PLLCFG_R] = 0U;
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pllcfg[PLLCFG_O] = PQR(1, 0, 0);
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for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) {
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unsigned long post_divm = input_freq / divm;
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unsigned int divp;
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if ((post_divm < POST_DIVM_MIN) || (post_divm > POST_DIVM_MAX)) {
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continue;
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}
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for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
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unsigned long long output_freq = freq_khz * 1000ULL;
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unsigned long long freq;
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unsigned long long divn;
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unsigned long long frac;
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unsigned int i;
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freq = output_freq * divm * (divp + 1U);
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divn = (freq / input_freq) - 1U;
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if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) {
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continue;
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}
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frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX);
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/* 2 loops to refine the fractional part */
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for (i = 2U; i != 0U; i--) {
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unsigned long long diff;
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unsigned long long vco;
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if (frac > FRAC_MAX) {
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break;
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}
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vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX);
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if ((vco < (VCO_MIN / 2U)) || (vco > (VCO_MAX / 2U))) {
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frac++;
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continue;
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}
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freq = vco / (divp + 1U);
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if (output_freq < freq) {
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diff = freq - output_freq;
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} else {
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diff = output_freq - freq;
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}
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if (diff < best_diff) {
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pllcfg[PLLCFG_M] = divm - 1U;
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pllcfg[PLLCFG_N] = (uint32_t)divn;
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pllcfg[PLLCFG_P] = divp;
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*fracv = (uint32_t)frac;
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if (diff == 0U) {
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return 0;
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}
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best_diff = diff;
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}
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frac++;
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}
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}
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}
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if (best_diff == ULLONG_MAX) {
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return -EINVAL;
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}
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return 0;
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}
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static int clk_get_pll1_settings(uint32_t clksrc, uint32_t freq_khz,
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uint32_t *pllcfg, uint32_t *fracv)
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{
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unsigned long input_freq = 0UL;
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assert(pllcfg != NULL);
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assert(fracv != NULL);
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switch (clksrc) {
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case CLK_PLL12_HSI:
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input_freq = stm32mp_clk_get_rate(CK_HSI);
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break;
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case CLK_PLL12_HSE:
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input_freq = stm32mp_clk_get_rate(CK_HSE);
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break;
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default:
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break;
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}
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if (input_freq == 0UL) {
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panic();
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}
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return clk_compute_pll1_settings(input_freq, freq_khz, pllcfg, fracv);
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}
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int stm32mp1_clk_init(void)
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{
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uintptr_t rcc_base = stm32mp_rcc_base();
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@ -1858,15 +1979,27 @@ int stm32mp1_clk_init(void)
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plloff[i] = fdt_rcc_subnode_offset(name);
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pllcfg_valid[i] = fdt_check_node(plloff[i]);
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if (!pllcfg_valid[i]) {
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if (pllcfg_valid[i]) {
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ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i],
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&pllfracv[i],
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pllcsg[i],
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&pllcsg_set[i]);
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if (ret != 0) {
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return ret;
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}
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continue;
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}
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ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i],
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&pllfracv[i], pllcsg[i],
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&pllcsg_set[i]);
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if (ret != 0) {
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return ret;
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if (i == _PLL1) {
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ret = clk_get_pll1_settings(clksrc[CLKSRC_PLL12],
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PLL1_NOMINAL_FREQ_IN_KHZ,
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pllcfg[i], &pllfracv[i]);
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if (ret != 0) {
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return ret;
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}
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pllcfg_valid[i] = true;
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}
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}
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@ -633,6 +633,11 @@ static inline uintptr_t tamp_bkpr(uint32_t idx)
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/* 2 FIXED */
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#define PLAT_NB_FIXED_REGUS U(2)
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/*******************************************************************************
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* STM32MP1 CLOCKS
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******************************************************************************/
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#define PLL1_NOMINAL_FREQ_IN_KHZ U(650000) /* 650MHz */
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/*******************************************************************************
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* Device Tree defines
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******************************************************************************/
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