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fix(st-clock): display proper PLL number for STM32MP13

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The PLL clk_id does not start at 0, but it is in the enum listing all
clocks. To have a better display of the PLL number, start at PLL1,
by changing pll->clk_id in messages with pll->clk_id - _CK_PLL1 + 1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ic09195ae6fe5f8d3a87e69962425f7c826f3670b
This commit is contained in:
Patrick Delaunay 2024-05-22 10:04:19 +02:00 • committed by Yann Gautier
parent f4a2bb986b
commit 039b7d4673
1 changed files with 4 additions and 4 deletions
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8
drivers/st/clk/clk-stm32mp13.c
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@ -1393,8 +1393,8 @@ static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv,
/* Wait PLL lock */
while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) == 0U) {
if (timeout_elapsed(timeout)) {
ERROR("%d clock start failed @ 0x%x: 0x%x\n",
pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base));
ERROR("PLL%d start failed @ 0x%x: 0x%x\n",
pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base));
return -EINVAL;
}
}
@ -1411,8 +1411,8 @@ static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv,
/* Wait PLL lock */
while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) != 0U) {
if (timeout_elapsed(timeout)) {
ERROR("%d clock stop failed @ 0x%x: 0x%x\n",
pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base));
ERROR("PLL%d stop failed @ 0x%x: 0x%x\n",
pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base));
return -EINVAL;
}
}