mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
refactor(st-clock): driver size optimization
Re-ordering structures to avoid gaps and minimize data. Reduce type of gate_refcounts[], uint8_t is enough. Re-ordering structures to avoid gaps and minimize data. Use an unsigned char to define a clock ops type. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Change-Id: I6b793dc34abdd6ef013609fc0f122da5d1824a34
This commit is contained in:
Gabriel Fernandez
Yann Gautier
parent
698bba5e74
commit
d9a7ddeb25
3 changed files with 100 additions and 52 deletions
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@ -224,6 +224,15 @@ const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id)
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return NULL;
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}
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static const struct stm32_clk_ops *_clk_get_ops(struct stm32_clk_priv *priv, int id)
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{
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const struct clk_stm32 *clk = _clk_get(priv, id);
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assert(clk->ops != NO_OPS);
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return priv->ops_array[clk->ops];
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}
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#define clk_div_mask(_width) GENMASK(((_width) - 1U), 0U)
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static unsigned int _get_table_div(const struct clk_div_table *table,
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@ -377,7 +386,7 @@ int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel
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int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int clk_id)
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{
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const struct clk_stm32 *clk = _clk_get(priv, clk_id);
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const struct stm32_clk_ops *ops = _clk_get_ops(priv, clk_id);
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const struct parent_cfg *parent;
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uint16_t mux_id;
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int sel;
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@ -394,8 +403,8 @@ int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int clk_id)
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mux_id &= MUX_PARENT_MASK;
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parent = &priv->parents[mux_id];
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if (clk->ops->get_parent != NULL) {
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sel = clk->ops->get_parent(priv, clk_id);
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if (ops->get_parent != NULL) {
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sel = ops->get_parent(priv, clk_id);
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} else {
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sel = clk_mux_get_parent(priv, mux_id);
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}
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@ -464,7 +473,7 @@ int clk_get_index(struct stm32_clk_priv *priv, unsigned long binding_id)
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unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id)
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{
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const struct clk_stm32 *clk = _clk_get(priv, id);
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const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
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int parent;
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if ((unsigned int)id >= priv->num) {
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@ -476,14 +485,14 @@ unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id)
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return 0UL;
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}
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if (clk->ops->recalc_rate != NULL) {
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if (ops->recalc_rate != NULL) {
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unsigned long prate = 0UL;
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if (parent != CLK_IS_ROOT) {
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prate = _clk_stm32_get_rate(priv, parent);
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}
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return clk->ops->recalc_rate(priv, id, prate);
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return ops->recalc_rate(priv, id, prate);
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}
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if (parent == CLK_IS_ROOT) {
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@ -520,10 +529,10 @@ bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag)
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int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id)
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{
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const struct clk_stm32 *clk = _clk_get(priv, id);
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const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
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if (clk->ops->enable != NULL) {
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clk->ops->enable(priv, id);
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if (ops->enable != NULL) {
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ops->enable(priv, id);
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}
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return 0;
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@ -550,7 +559,7 @@ static int _clk_stm32_enable_core(struct stm32_clk_priv *priv, int id)
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priv->gate_refcounts[id]++;
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if (priv->gate_refcounts[id] == UINT_MAX) {
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if (priv->gate_refcounts[id] == UINT8_MAX) {
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ERROR("%s: %d max enable count !", __func__, id);
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panic();
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}
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@ -571,10 +580,10 @@ int _clk_stm32_enable(struct stm32_clk_priv *priv, int id)
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void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id)
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{
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const struct clk_stm32 *clk = _clk_get(priv, id);
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const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
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if (clk->ops->disable != NULL) {
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clk->ops->disable(priv, id);
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if (ops->disable != NULL) {
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ops->disable(priv, id);
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}
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}
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@ -619,10 +628,10 @@ void _clk_stm32_disable(struct stm32_clk_priv *priv, int id)
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bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id)
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{
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const struct clk_stm32 *clk = _clk_get(priv, id);
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const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
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if (clk->ops->is_enabled != NULL) {
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return clk->ops->is_enabled(priv, id);
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if (ops->is_enabled != NULL) {
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return ops->is_enabled(priv, id);
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}
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return priv->gate_refcounts[id];
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@ -1081,12 +1090,10 @@ int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base)
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priv->base = base;
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for (i = 0U; i < priv->num; i++) {
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const struct clk_stm32 *clk = _clk_get(priv, i);
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const struct stm32_clk_ops *ops = _clk_get_ops(priv, i);
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assert(clk->ops != NULL);
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if (clk->ops->init != NULL) {
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clk->ops->init(priv, i);
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if (ops->init != NULL) {
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ops->init(priv, i);
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}
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
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* Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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@ -21,23 +21,23 @@ struct gate_cfg {
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};
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struct clk_div_table {
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unsigned int val;
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unsigned int div;
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uint16_t val;
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uint16_t div;
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};
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struct div_cfg {
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const struct clk_div_table *table;
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uint16_t offset;
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uint8_t shift;
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uint8_t width;
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uint8_t flags;
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uint8_t bitrdy;
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const struct clk_div_table *table;
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};
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struct parent_cfg {
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uint8_t num_parents;
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const uint16_t *id_parents;
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struct mux_cfg *mux;
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uint8_t num_parents;
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};
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struct stm32_clk_priv;
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@ -56,9 +56,9 @@ struct stm32_clk_ops {
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struct clk_stm32 {
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uint16_t binding;
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uint16_t parent;
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uint8_t ops;
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uint8_t flags;
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void *clock_cfg;
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const struct stm32_clk_ops *ops;
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};
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struct stm32_clk_priv {
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@ -73,8 +73,9 @@ struct stm32_clk_priv {
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const uint32_t nb_div;
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struct clk_oscillator_data *osci_data;
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const uint32_t nb_osci_data;
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uint32_t *gate_refcounts;
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uint8_t *gate_refcounts;
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void *pdata;
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const struct stm32_clk_ops **ops_array;
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};
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struct stm32_clk_bypass {
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@ -97,13 +98,14 @@ struct stm32_clk_drive {
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struct clk_oscillator_data {
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const char *name;
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uint16_t id_clk;
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unsigned long frequency;
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uint16_t gate_id;
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uint16_t gate_rdy_id;
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struct stm32_clk_bypass *bypass;
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struct stm32_clk_css *css;
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struct stm32_clk_drive *drive;
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unsigned long frequency;
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uint16_t id_clk;
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uint16_t gate_id;
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uint16_t gate_rdy_id;
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};
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struct clk_fixed_rate {
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@ -218,7 +220,7 @@ void clk_stm32_display_clock_info(void);
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#endif
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struct clk_stm32_div_cfg {
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int id;
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uint8_t id;
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};
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#define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \
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@ -229,11 +231,11 @@ struct clk_stm32_div_cfg {
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.clock_cfg = &(struct clk_stm32_div_cfg){\
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.id = (_div_id),\
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},\
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.ops = &clk_stm32_divider_ops,\
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.ops = STM32_DIVIDER_OPS,\
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}
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struct clk_stm32_gate_cfg {
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int id;
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uint8_t id;
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};
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#define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \
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@ -244,12 +246,12 @@ struct clk_stm32_gate_cfg {
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.clock_cfg = &(struct clk_stm32_gate_cfg){\
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.id = (_gate_id),\
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},\
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.ops = &clk_stm32_gate_ops,\
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.ops = STM32_GATE_OPS,\
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}
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struct fixed_factor_cfg {
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unsigned int mult;
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unsigned int div;
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uint8_t mult;
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uint8_t div;
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};
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unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv,
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@ -263,7 +265,7 @@ unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv,
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.mult = (_mult),\
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.div = (_div),\
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},\
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.ops = &clk_fixed_factor_ops,\
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.ops = FIXED_FACTOR_OPS,\
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}
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#define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \
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@ -275,7 +277,7 @@ unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv,
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.offset = (_offset),\
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.bit_idx = (_bit_idx),\
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},\
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.ops = &clk_gate_ops,\
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.ops = GATE_OPS,\
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}
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#define STM32_MUX(idx, _binding, _mux_id, _flags) \
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@ -284,7 +286,7 @@ unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv,
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.parent = (MUX(_mux_id)),\
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.flags = (_flags),\
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.clock_cfg = NULL,\
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.ops = (&clk_mux_ops),\
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.ops = STM32_MUX_OPS\
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}
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struct clk_timer_cfg {
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@ -301,7 +303,7 @@ struct clk_timer_cfg {
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.apbdiv = (_apbdiv),\
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.timpre = (_timpre),\
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},\
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.ops = &clk_timer_ops,\
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.ops = STM32_TIMER_OPS,\
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}
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struct clk_stm32_fixed_rate_cfg {
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@ -315,7 +317,7 @@ struct clk_stm32_fixed_rate_cfg {
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.clock_cfg = &(struct clk_stm32_fixed_rate_cfg){\
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.rate = (_rate),\
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},\
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.ops = &clk_stm32_fixed_rate_ops,\
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.ops = STM32_FIXED_RATE_OPS,\
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}
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#define BYPASS(_offset, _bit_byp, _bit_digbyp) &(struct stm32_clk_bypass){\
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@ -355,7 +357,7 @@ int clk_stm32_osc_gate_enable(struct stm32_clk_priv *priv, int id);
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void clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id);
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struct stm32_osc_cfg {
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int osc_id;
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uint8_t osc_id;
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};
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#define CLK_OSC(idx, _idx, _parent, _osc_id) \
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@ -366,7 +368,7 @@ struct stm32_osc_cfg {
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.clock_cfg = &(struct stm32_osc_cfg){\
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.osc_id = (_osc_id),\
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},\
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.ops = &clk_stm32_osc_ops,\
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.ops = STM32_OSC_OPS,\
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}
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#define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \
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@ -377,7 +379,7 @@ struct stm32_osc_cfg {
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.clock_cfg = &(struct stm32_osc_cfg){\
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.osc_id = (_osc_id),\
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},\
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.ops = &clk_stm32_osc_nogate_ops,\
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.ops = STM32_OSC_NOGATE_OPS,\
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}
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extern const struct stm32_clk_ops clk_mux_ops;
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@ -390,4 +392,19 @@ extern const struct stm32_clk_ops clk_stm32_fixed_rate_ops;
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extern const struct stm32_clk_ops clk_stm32_osc_ops;
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extern const struct stm32_clk_ops clk_stm32_osc_nogate_ops;
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enum {
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NO_OPS,
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FIXED_FACTOR_OPS,
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GATE_OPS,
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STM32_MUX_OPS,
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STM32_DIVIDER_OPS,
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STM32_GATE_OPS,
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STM32_TIMER_OPS,
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STM32_FIXED_RATE_OPS,
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STM32_OSC_OPS,
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STM32_OSC_NOGATE_OPS,
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STM32_LAST_OPS
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};
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#endif /* CLK_STM32_CORE_H */
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@ -889,7 +889,7 @@ static bool pll4_bootrom;
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#endif
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/* RCC clock device driver private */
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static unsigned int refcounts_mp13[CK_LAST];
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static uint8_t refcounts_mp13[CK_LAST];
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static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx);
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@ -1693,7 +1693,7 @@ static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx)
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}
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struct stm32_pll_cfg {
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int pll_id;
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uint8_t pll_id;
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};
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static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id,
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@ -1775,12 +1775,12 @@ static const struct stm32_clk_ops clk_stm32_pll_ops = {
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.clock_cfg = &(struct stm32_pll_cfg) {\
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.pll_id = _pll_id,\
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},\
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.ops = &clk_stm32_pll_ops,\
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.ops = STM32_PLL_OPS,\
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}
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struct clk_stm32_composite_cfg {
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int gate_id;
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int div_id;
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uint8_t gate_id;
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uint8_t div_id;
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};
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static unsigned long clk_stm32_composite_recalc_rate(struct stm32_clk_priv *priv,
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@ -1832,9 +1832,32 @@ static const struct stm32_clk_ops clk_stm32_composite_ops = {
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.gate_id = (_gate_id),\
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.div_id = (_div_id),\
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},\
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.ops = &clk_stm32_composite_ops,\
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.ops = STM32_COMPOSITE_OPS,\
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}
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enum {
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STM32_PLL_OPS = STM32_LAST_OPS,
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STM32_COMPOSITE_OPS,
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MP13_LAST_OPS
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};
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static const struct stm32_clk_ops *ops_array_mp13[MP13_LAST_OPS] = {
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[NO_OPS] = NULL,
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[FIXED_FACTOR_OPS] = &clk_fixed_factor_ops,
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[GATE_OPS] = &clk_gate_ops,
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[STM32_MUX_OPS] = &clk_mux_ops,
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[STM32_DIVIDER_OPS] = &clk_stm32_divider_ops,
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[STM32_GATE_OPS] = &clk_stm32_gate_ops,
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[STM32_TIMER_OPS] = &clk_timer_ops,
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[STM32_FIXED_RATE_OPS] = &clk_stm32_fixed_rate_ops,
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[STM32_OSC_OPS] = &clk_stm32_osc_ops,
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[STM32_OSC_NOGATE_OPS] = &clk_stm32_osc_nogate_ops,
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[STM32_PLL_OPS] = &clk_stm32_pll_ops,
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[STM32_COMPOSITE_OPS] = &clk_stm32_composite_ops
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};
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static const struct clk_stm32 stm32mp13_clk[CK_LAST] = {
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/* ROOT CLOCKS */
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CLK_FIXED_RATE(_CK_OFF, _NO_ID, 0),
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@ -1994,6 +2017,7 @@ static struct stm32_clk_priv stm32mp13_clock_data = {
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.nb_osci_data = ARRAY_SIZE(stm32mp13_osc_data),
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.gate_refcounts = refcounts_mp13,
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.pdata = &stm32mp13_clock_pdata,
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.ops_array = ops_array_mp13,
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};
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static int stm32mp1_init_clock_tree(void)
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