When fdt_add_reserved_memory() is called to add a memory region, we
unconditionally add a node for that region. However there might be an
existing region node in the DT already, or there might be an overlapping
region. The Linux kernel will complain in those cases.
Cover the simple case of the region already existing in the DT, as this
is what we actually see on the Allwinner H616: The mainline DT contains
a node reserving the memory for TF-A, in case the DT changed by TF-A
itself is not given to the kernel. Our code always adds a region, making
the kernel complain - albeit without further consequences.
Covering all cases of overlapping regions would blow up the generic DT
code too much, so just add a simple check for an existing region
completely containing the to-be-added region, simply bailing out in this
case.
This prevents the kernel warning for the Allwinner H616.
This code requires a function from fdt_wrappers.c, so we have to include
that file for platforms that use the fdt_add_reserved_memory() function
(rpi4 and versal2).
Change-Id: I98404889163316addbb42130d7177f1a21c8be06
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* changes:
feat(tc): bind DPU SMMU on TC4
feat(tc): bind GPU SMMU on TC4
feat(tc): update DT for Drage GPU
feat(tc): enable SME and SME2 options for TC4
feat(tc): add new TC4 RoS definitions
feat(tc): add system generic timer register definition for TC4
feat(tc): allow TARGET_VERSION=4
feat(tc): add MHUv3 register addresses for TC4
feat(tc): add device tree binding for TC4
TC4 adds a new SMMU-700 specifically for the DPU (in the RoS). This is
used as the DPU SMMU instead of the existing SMMU used for both the GPU
and DPU. Update the devicetree to reflect this.
Note that the streamID values have also changes for this new SMMU. This
is because TC4 also updates the new SMMU to use a different streamID for
each DPU port - these must all be added to the device tree.
Change-Id: If2ce9749e40937fd1291346d071b691cfb662f2e
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
A SMMU-700 is used on TC4 for only GPU, on both FVP and FPGA. Add DT
binding for it.
Change-Id: I1b840676fd02c3961d4efdd769f12a4b01d459fb
Signed-off-by: Leo Yan <leo.yan@arm.com>
This patch incorporates the changes for Drage GPU to uses new access
window interface "IRQ_AW". As the interrupt properties are different
between TC4 and other TC platforms, this patch appends the interrupt
properties in platform specific DT binding file.
Change-Id: I2ca505846f03ce64b8e5f02fd202962dbfe39f25
Signed-off-by: Leo Yan <leo.yan@arm.com>
Set the Make flags for TF-A to be able to enable SME and SME2 features.
Note that we enable these architectural features for both the secure and
non-secure worlds, which is required on TC4.
In the case of the non-secure world, we specify a value of 2 for the
flag which specifies that TF-A should check the feature register to
ensure that the feature is present before enabling it. This allows these
flags to be compatible with all platforms and stops TF-A doing anything
different if it does not detect that the feature is present.
Change-Id: I51f8c7e3eb1cf06767f4b155c93269e1f129f730
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
The TC4 uses a new RoS (Virtual Peripherals) and places them at
different address to that in TC3. Add these addresses to the DTS.
Change-Id: Ia62a670e47cdc98b3c113a670a21edc65905cafe
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Add new include (specific to TC4) to the TC platform file which
specifies the system generic timer base address and is used by the TF-a
for use as system counters.
Note that this include must come before arm_def.h. This is required
as it checks if ARM_SYS_CNTCTL macros are defined before defining
its own macros.
Change-Id: I56861e5737271b29f09c75d962533be620766b52
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Add basic support for TARGET_VERSION=4. It extends the existing 'if'
statements in the Makefile and the header to allow them to take the
value of 4 and also specifies the SCMI platform info to use for TC4.
Change-Id: I8d8257671314277a133e88ef65fae8fada93d00e
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Since TC3 and TC4 share most components in the hardware design, they can
reuse the device tree binding. For this reason, this patch extracts the
common modules from tc3.dts and put into the file tc3-4-based.dtsi.
As a result, a new created tc4.dts file includes tc3-4-based.dtsi for
support DT binding for the TC4 platform.
Change-Id: Ib7497162cb131d94a722aeaa14a1a37fb0095829
Signed-off-by: Leo Yan <leo.yan@arm.com>
This change fixes several breakages that were introduced in some build
configurations by the introduction of the cot-dt2c tool.
Some Python environments cannot be managed directly via `pip`, and
invocations of `make`, including `make distclean`, would cause errors
along the lines of:
error: externally-managed-environment
× This environment is externally managed
╰─> To install Python packages system-wide, try apt install
python3-xyz, where xyz is the package you are trying to
install.
This change has been resolved by ensuring that calls to the cot-dt2c
tool from the build system happen exclusively through Poetry, which
automatically sets up a virtual environment that *can* be modified.
Some environments saw the following error when building platforms where
the cot-dt2c tool was used:
make: *** No rule to make target '<..>/debug/bl2_cot.c', needed
by '<..>/debug/bl2/bl2_cot.o'. Stop.
Additionally, environments with a more recent version of Python saw the
following error:
File "<...>/lib/python3.12/site-packages/cot_dt2c/cot_parser.py",
line 637, in img_to_c
if ifdef:
^^^^^
NameError: name 'ifdef' is not defined
Both of these errors have now been resolved by modifications to the
build system and the cot-dt2c tool to enable preprocessing of the device
tree source file before it is processed by the tool.
As a consequence of this change, the `pydevicetree` library is no longer
vendored into the repository tree, and we instead pull it in via a
dependency in Poetry.
This change also resolves several MyPy warnings and errors related to
missing type hints.
Change-Id: I72b2d01caca3fcb789d3fe2549f318a9c92d77d1
Signed-off-by: Chris Kay <chris.kay@arm.com>
Use sysctrl module rather than watchdog0 to reset the entire system.
Sysctrl is more reliable and requires less resources such as clocks and
resets. Doing this also allows non-secure OS to use the watchdog.
Change-Id: I30ac2780cc70055d81b35e55e35c9cb7f58b40cc
Signed-off-by: Yang Xiwen <forbidden405@foxmail.com>
I originally added myself here because I had experience with the rk3399
code, when there were no other maintainers and that was the only
supported Rockchip SoC. Nowadays there are maintainers from the actual
manufacturer and most changes concern other SoCs, so I don't think it
makes sense for me to still be on here.
Change-Id: Id75089e62cf1a8b4cf1a27903808922968520636
Signed-off-by: Julius Werner <jwerner@chromium.org>
Update the test files to eliminate the use of preprocessor macros,
as the tool now requires processed output. The documentation has
also been revised accordingly.
Additionally, remove the Device Tree Source test files that were
added to test the #ifdef conditions.
Change-Id: I13a682db20e5e44170fc25a2e2dbedd45b9c7321
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
When trying to build for the Corstone-1000 platform without specifying a
valid TARGET_PLATFORM value, the "make" call reports a Makefile error
instead of the expected error messages pointing to the variable
omission:
====================
platform.mk: *** recipe commences before first target. Stop.
====================
This is due to the make's infamous special handling of the tab
character.
Fix the error report by replacing the tab with spaces.
Change-Id: I38264b6731793e5d5b929c189bb963e55bd5ce2d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
You can only bind a limited number of events in each range. If you
attempt to bind more, it was crashing. This patch makes it return an
error code instead.
Change-Id: Ib19f0f0780959ded244d45349d9d6c8607255c15
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>
This patch is to add in missing ECC register (INITSTAT)
Change-Id: Iecf03dc9597ec2884901c132fb9cef7e90ab06a0
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Previously the max GPT block size was set to 2MB as a conservative
default. For workloads making use of SMMU in Normal world, and has
a Stage 2 block mapping of large sizes like 512MB or 1GB, then a
max GPT block size of 2MB may result in performance regression.
Hence this patch changes the default max GPT block size from 2MB to 512MB.
Change-Id: If90f12f494ec0f44d3e5974df8d58fcb528cfd34
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Changed reg_clr to use the base address + RPI3_GPIO_GPCLR,
this corrects the reg_clr address.
Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
Signed-off-by: Abhi Singh <abhi.singh@arm.com>
Change-Id: I9ca50905efd4c640f143783c5a00676b246a2e26
Currently, as part of the context_memory report, we explicitly
list the EL3, EL1 and EL2 registers and memory usage per CPU
for each world. The remaining bits in the cpu_context_t structure
are grouped and listed as other section.
This patch enhances this part, by individually listing all the
remaining bits (GPREGS, PAUTH_REGS) separately providing
a much detailed overview of the context memory consumption
amongst the registers.
The patch has been tested on the CI with the following patch
and the results are summarised precisely.
[https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/28849]
Change-Id: I16f210b605ddd7900600519520accf1ccd057bc7
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure, we hold a copy of EL1, EL2
system registers, per world per PE. This context structure is
enormous and will continue to grow bigger with the addition of
new features incorporating new registers.
* Ideally, EL3 should save and restore the system registers at its next
lower exception level, which is EL2 in majority of the configurations.
* This patch aims at optimising the memory allocation in cases, when
the members from the context structure are unused. So el1 system
register context must be omitted when lower EL is always x-EL2.
* "CTX_INCLUDE_EL2_REGS" is the internal build flag which gets set,
when SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1.
It indicates, the system registers at EL2 are context switched for
the respective build configuration. Here, there is no need to save
and restore EL1 system registers, while x-EL2 is enabled.
Henceforth, this patch addresses this issue, by taking out the EL1
context at all possible places, while EL2 (CTX_INCLUDE_EL2_REGS) is
enabled, there by saving memory.
Change-Id: Ifddc497d3c810e22a15b1c227a731bcc133c2f4a
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to write and read into these context entries, looks
repetitive and is invoked at most places.
This section is refactored to bring them under a static procedure,
keeping the code neat and easier to maintain.
Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): add Cactus partition manifest for EL3 SPMC
chore(simd): remove unused macros and utilities for FP
feat(el3-spmc): support simd context management upon world switch
feat(trusty): switch to simd_ctx_save/restore apis
feat(pncd): switch to simd_ctx_save/restore apis
feat(spm-mm): switch to simd_ctx_save/restore APIs
feat(simd): add rules to rationalize simd ctxt mgmt
feat(simd): introduce simd context helper APIs
feat(simd): add routines to save, restore sve state
feat(simd): add sve state to simd ctxt struct
feat(simd): add data struct for simd ctxt management
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.
Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or FXOSC oscillators. It has eight outputs (PHIs) and
their frequencies can be controlled programmatically using output
dividers. An additional output clocks the PERIPH DFS using the VCO
frequency of the PERIPH PLL.
Change-Id: I637294b2da94f35e95dc1750dad36c129a276bb9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
