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Merge changes from topic "clean-up-errata-compatibility" into integration

Browse source 
* changes:
  refactor(cpus): remove cpu specific errata funcs
  refactor(cpus): directly invoke errata reporter
This commit is contained in:
Manish V Badarkhe 2024-08-27 16:23:58 +02:00 • committed by TrustedFirmware Code Review
commit cc4f383863
62 changed files with 51 additions and 423 deletions
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63
include/lib/cpus/aarch32/cpu_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -115,11 +115,6 @@
.popsection
.endif
/*
* Mandatory errata status printing function for CPUs of
* this class.
*/
.word \_name\()_errata_report
.word \_name\()_cpu_str
#ifdef IMAGE_BL32
@ -130,45 +125,6 @@
#endif
.endm
#if REPORT_ERRATA
/*
* Print status of a CPU errata
*
* _chosen:
* Identifier indicating whether or not a CPU errata has been
* compiled in.
* _cpu:
* Name of the CPU
* _id:
* Errata identifier
* _rev_var:
* Register containing the combined value CPU revision and variant
* - typically the return value of cpu_get_rev_var
*/
.macro report_errata _chosen, _cpu, _id, _rev_var=r4
/* Stash a string with errata ID */
.pushsection .rodata
\_cpu\()_errata_\_id\()_str:
.asciz "\_id"
.popsection
/* Check whether errata applies */
mov r0, \_rev_var
bl check_errata_\_id
.ifeq \_chosen
/*
* Errata workaround has not been compiled in. If the errata would have
* applied had it been compiled in, print its status as missing.
*/
cmp r0, #0
movne r0, #ERRATA_MISSING
.endif
ldr r1, =\_cpu\()_cpu_str
ldr r2, =\_cpu\()_errata_\_id\()_str
bl errata_print_msg
.endm
#endif
/*
* Helper macro that reads the part number of the current CPU and jumps
* to the given label if it matches the CPU MIDR provided.
@ -239,21 +195,4 @@
.popsection
.endm
/*
* Maintain compatibility with the old scheme of "each cpu has its own reporter".
* TODO remove entirely once all cpus have been converted. This includes the
* cpu_ops entry, as print_errata_status can call this directly for all cpus
*/
.macro errata_report_shim _cpu:req
#if REPORT_ERRATA
func \_cpu\()_errata_report
push {r12, lr}
bl generic_errata_report
pop {r12, lr}
bx lr
endfunc \_cpu\()_errata_report
#endif
.endm
#endif /* CPU_MACROS_S */

68
include/lib/cpus/aarch64/cpu_macros.S
View file

@ -132,12 +132,6 @@
.popsection
.endif
/*
* Mandatory errata status printing function for CPUs of
* this class.
*/
.quad \_name\()_errata_report
.quad \_name\()_cpu_str
#ifdef IMAGE_BL31
@ -171,49 +165,6 @@
\_extra1, \_extra2, \_extra3, 0, \_power_down_ops
.endm
/* TODO can be deleted once all CPUs have been converted */
#if REPORT_ERRATA
/*
* Print status of a CPU errata
*
* _chosen:
* Identifier indicating whether or not a CPU errata has been
* compiled in.
* _cpu:
* Name of the CPU
* _id:
* Errata identifier
* _rev_var:
* Register containing the combined value CPU revision and variant
* - typically the return value of cpu_get_rev_var
*/
.macro report_errata _chosen, _cpu, _id, _rev_var=x8
/* Stash a string with errata ID */
.pushsection .rodata
\_cpu\()_errata_\_id\()_str:
.asciz "\_id"
.popsection
/* Check whether errata applies */
mov x0, \_rev_var
/* Shall clobber: x0-x7 */
bl check_errata_\_id
.ifeq \_chosen
/*
* Errata workaround has not been compiled in. If the errata would have
* applied had it been compiled in, print its status as missing.
*/
cbz x0, 900f
mov x0, #ERRATA_MISSING
.endif
900:
adr x1, \_cpu\()_cpu_str
adr x2, \_cpu\()_errata_\_id\()_str
bl errata_print_msg
.endm
#endif
/*
* This macro is used on some CPUs to detect if they are vulnerable
* to CVE-2017-5715.
@ -622,23 +573,4 @@
endfunc \_cpu\()_reset_func
.endm
/*
* Maintain compatibility with the old scheme of each cpu has its own reporting.
* TODO remove entirely once all cpus have been converted. This includes the
* cpu_ops entry, as print_errata_status can call this directly for all cpus
*/
.macro errata_report_shim _cpu:req
#if REPORT_ERRATA
func \_cpu\()_errata_report
/* normal stack frame for pretty debugging */
stp x29, x30, [sp, #-16]!
mov x29, sp
bl generic_errata_report
ldp x29, x30, [sp], #16
ret
endfunc \_cpu\()_errata_report
#endif
.endm
#endif /* CPU_MACROS_S */

8
include/lib/cpus/cpu_ops.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -57,7 +57,6 @@
#define CPU_ERRATA_LIST_END_SIZE CPU_WORD_SIZE
/* Fields required to print errata status */
#if REPORT_ERRATA
#define CPU_ERRATA_FUNC_SIZE CPU_WORD_SIZE
#define CPU_CPU_STR_SIZE CPU_WORD_SIZE
/* BL1 doesn't require mutual exclusion and printed flag. */
#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
@ -68,7 +67,6 @@
#define CPU_ERRATA_PRINTED_SIZE 0
#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */
#else
#define CPU_ERRATA_FUNC_SIZE 0
#define CPU_CPU_STR_SIZE 0
#define CPU_ERRATA_LOCK_SIZE 0
#define CPU_ERRATA_PRINTED_SIZE 0
@ -98,8 +96,7 @@
#endif /* __aarch64__ */
#define CPU_ERRATA_LIST_START CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
#define CPU_ERRATA_LIST_END CPU_ERRATA_LIST_START + CPU_ERRATA_LIST_START_SIZE
#define CPU_ERRATA_FUNC CPU_ERRATA_LIST_END + CPU_ERRATA_LIST_END_SIZE
#define CPU_CPU_STR CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
#define CPU_CPU_STR CPU_ERRATA_LIST_END + CPU_ERRATA_LIST_END_SIZE
#define CPU_ERRATA_LOCK CPU_CPU_STR + CPU_CPU_STR_SIZE
#define CPU_ERRATA_PRINTED CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
#if __aarch64__
@ -130,7 +127,6 @@ struct cpu_ops {
void *errata_list_start;
void *errata_list_end;
#if REPORT_ERRATA
void (*errata_func)(void);
char *cpu_str;
#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
spinlock_t *errata_lock;

3
include/lib/cpus/errata.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -34,7 +34,6 @@
#include <lib/cassert.h>
void print_errata_status(void);
void errata_print_msg(unsigned int status, const char *cpu, const char *id);
#if ERRATA_A520_2938996 || ERRATA_X4_2726228
unsigned int check_if_affected_core(void);

10
lib/cpus/aarch32/aem_generic.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -40,14 +40,6 @@ func aem_generic_cluster_pwr_dwn
b dcsw_op_all
endfunc aem_generic_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for AEM. Must follow AAPCS.
*/
func aem_generic_errata_report
bx lr
endfunc aem_generic_errata_report
#endif
/* cpu_ops for Base AEM FVP */
declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \

4
lib/cpus/aarch32/cortex_a12.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -73,8 +73,6 @@ func cortex_a12_cluster_pwr_dwn
b cortex_a12_disable_smp
endfunc cortex_a12_cluster_pwr_dwn
errata_report_shim cortex_a12
declare_cpu_ops cortex_a12, CORTEX_A12_MIDR, \
cortex_a12_reset_func, \
cortex_a12_core_pwr_dwn, \

4
lib/cpus/aarch32/cortex_a15.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -172,8 +172,6 @@ func cortex_a15_cluster_pwr_dwn
b cortex_a15_disable_smp
endfunc cortex_a15_cluster_pwr_dwn
errata_report_shim cortex_a15
declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \
cortex_a15_reset_func, \
cortex_a15_core_pwr_dwn, \

4
lib/cpus/aarch32/cortex_a17.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -106,8 +106,6 @@ endfunc check_errata_cve_2017_5715
add_erratum_entry cortex_a17, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
errata_report_shim cortex_a17
func cortex_a17_reset_func
mov r5, lr
bl cpu_get_rev_var

4
lib/cpus/aarch32/cortex_a32.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -117,8 +117,6 @@ func cortex_a32_cluster_pwr_dwn
b cortex_a32_disable_smp
endfunc cortex_a32_cluster_pwr_dwn
errata_report_shim cortex_a32
declare_cpu_ops cortex_a32, CORTEX_A32_MIDR, \
cortex_a32_reset_func, \
cortex_a32_core_pwr_dwn, \

4
lib/cpus/aarch32/cortex_a5.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -69,8 +69,6 @@ func cortex_a5_cluster_pwr_dwn
b cortex_a5_disable_smp
endfunc cortex_a5_cluster_pwr_dwn
errata_report_shim cortex_a5
declare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \
cortex_a5_reset_func, \
cortex_a5_core_pwr_dwn, \

4
lib/cpus/aarch32/cortex_a53.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -297,8 +297,6 @@ func cortex_a53_cluster_pwr_dwn
b cortex_a53_disable_smp
endfunc cortex_a53_cluster_pwr_dwn
errata_report_shim cortex_a53
declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
cortex_a53_reset_func, \
cortex_a53_core_pwr_dwn, \

4
lib/cpus/aarch32/cortex_a57.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -606,8 +606,6 @@ func cortex_a57_cluster_pwr_dwn
b cortex_a57_disable_ext_debug
endfunc cortex_a57_cluster_pwr_dwn
errata_report_shim cortex_a57
declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \
cortex_a57_reset_func, \
cortex_a57_core_pwr_dwn, \

4
lib/cpus/aarch32/cortex_a7.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -73,8 +73,6 @@ func cortex_a7_cluster_pwr_dwn
b cortex_a7_disable_smp
endfunc cortex_a7_cluster_pwr_dwn
errata_report_shim cortex_a7
declare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \
cortex_a7_reset_func, \
cortex_a7_core_pwr_dwn, \

4
lib/cpus/aarch32/cortex_a72.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -256,8 +256,6 @@ func cortex_a72_cluster_pwr_dwn
b cortex_a72_disable_ext_debug
endfunc cortex_a72_cluster_pwr_dwn
errata_report_shim cortex_a72
declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
cortex_a72_reset_func, \
cortex_a72_core_pwr_dwn, \

4
lib/cpus/aarch32/cortex_a9.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -57,8 +57,6 @@ endfunc check_errata_cve_2017_5715
add_erratum_entry cortex_a9, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
errata_report_shim cortex_a9
func cortex_a9_reset_func
#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
ldr r0, =wa_cve_2017_5715_bpiall_vbar

9
lib/cpus/aarch64/a64fx.S
View file

@ -16,15 +16,6 @@ endfunc a64fx_core_pwr_dwn
func a64fx_cluster_pwr_dwn
endfunc a64fx_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for A64FX. Must follow AAPCS.
*/
func a64fx_errata_report
ret
endfunc a64fx_errata_report
#endif
/* ---------------------------------------------
* This function provides cpu specific
* register information for crash reporting.

11
lib/cpus/aarch64/aem_generic.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -74,15 +74,6 @@ func aem_generic_cluster_pwr_dwn
b dcsw_op_all
endfunc aem_generic_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for AEM. Must follow AAPCS.
*/
func aem_generic_errata_report
ret
endfunc aem_generic_errata_report
#endif
/* ---------------------------------------------
* This function provides cpu specific
* register information for crash reporting.

4
lib/cpus/aarch64/cortex_a35.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -111,8 +111,6 @@ func cortex_a35_cluster_pwr_dwn
b cortex_a35_disable_smp
endfunc cortex_a35_cluster_pwr_dwn
errata_report_shim cortex_a35
/* ---------------------------------------------
* This function provides cortex_a35 specific
* register information for crash reporting.

4
lib/cpus/aarch64/cortex_a510.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, Arm Limited. All rights reserved.
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -204,8 +204,6 @@ func cortex_a510_core_pwr_dwn
ret
endfunc cortex_a510_core_pwr_dwn
errata_report_shim cortex_a510
cpu_reset_func_start cortex_a510
/* Disable speculative loads */
msr SSBS, xzr

2
lib/cpus/aarch64/cortex_a520.S
View file

@ -68,8 +68,6 @@ func cortex_a520_core_pwr_dwn
ret
endfunc cortex_a520_core_pwr_dwn
errata_report_shim cortex_a520
cpu_reset_func_start cortex_a520
/* Disable speculative loads */
msr SSBS, xzr

4
lib/cpus/aarch64/cortex_a53.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -199,8 +199,6 @@ func cortex_a53_cluster_pwr_dwn
b cortex_a53_disable_smp
endfunc cortex_a53_cluster_pwr_dwn
errata_report_shim cortex_a53
/* ---------------------------------------------
* This function provides cortex_a53 specific
* register information for crash reporting.

4
lib/cpus/aarch64/cortex_a55.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -116,8 +116,6 @@ add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_
cpu_reset_func_start cortex_a55
cpu_reset_func_end cortex_a55
errata_report_shim cortex_a55
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------

4
lib/cpus/aarch64/cortex_a57.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -284,8 +284,6 @@ func cortex_a57_cluster_pwr_dwn
b cortex_a57_disable_ext_debug
endfunc cortex_a57_cluster_pwr_dwn
errata_report_shim cortex_a57
/* ---------------------------------------------
* This function provides cortex_a57 specific
* register information for crash reporting.

22
lib/cpus/aarch64/cortex_a65.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -45,26 +45,6 @@ func cortex_a65_cpu_pwr_dwn
ret
endfunc cortex_a65_cpu_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex-A65. Must follow AAPCS.
*/
func cortex_a65_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_DSU_936184, cortex_a65, dsu_936184
ldp x8, x30, [sp], #16
ret
endfunc cortex_a65_errata_report
#endif
.section .rodata.cortex_a65_regs, "aS"
cortex_a65_regs: /* The ascii list of register names to be reported */

4
lib/cpus/aarch64/cortex_a65ae.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -41,8 +41,6 @@ func cortex_a65ae_cpu_pwr_dwn
ret
endfunc cortex_a65ae_cpu_pwr_dwn
errata_report_shim cortex_a65ae
.section .rodata.cortex_a65ae_regs, "aS"
cortex_a65ae_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""

4
lib/cpus/aarch64/cortex_a710.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -229,8 +229,6 @@ func cortex_a710_core_pwr_dwn
ret
endfunc cortex_a710_core_pwr_dwn
errata_report_shim cortex_a710
cpu_reset_func_start cortex_a710
/* Disable speculative loads */
msr SSBS, xzr

2
lib/cpus/aarch64/cortex_a715.S
View file

@ -148,8 +148,6 @@ func cortex_a715_core_pwr_dwn
ret
endfunc cortex_a715_core_pwr_dwn
errata_report_shim cortex_a715
/* ---------------------------------------------
* This function provides Cortex-A715 specific
* register information for crash reporting.

4
lib/cpus/aarch64/cortex_a72.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -271,8 +271,6 @@ func cortex_a72_cluster_pwr_dwn
b cortex_a72_disable_ext_debug
endfunc cortex_a72_cluster_pwr_dwn
errata_report_shim cortex_a72
/* ---------------------------------------------
* This function provides cortex_a72 specific
* register information for crash reporting.

2
lib/cpus/aarch64/cortex_a720.S
View file

@ -92,8 +92,6 @@ func cortex_a720_core_pwr_dwn
ret
endfunc cortex_a720_core_pwr_dwn
errata_report_shim cortex_a720
/* ---------------------------------------------
* This function provides Cortex A720-specific
* register information for crash reporting.

2
lib/cpus/aarch64/cortex_a725.S
View file

@ -40,8 +40,6 @@ func cortex_a725_core_pwr_dwn
ret
endfunc cortex_a725_core_pwr_dwn
errata_report_shim cortex_a725
/* ---------------------------------------------
* This function provides Cortex-A725 specific
* register information for crash reporting.

5
lib/cpus/aarch64/cortex_a73.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -178,9 +178,6 @@ func cortex_a73_cluster_pwr_dwn
b cortex_a73_disable_smp
endfunc cortex_a73_cluster_pwr_dwn
errata_report_shim cortex_a73
/* ---------------------------------------------
* This function provides cortex_a73 specific
* register information for crash reporting.

4
lib/cpus/aarch64/cortex_a75.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -146,8 +146,6 @@ func cortex_a75_core_pwr_dwn
ret
endfunc cortex_a75_core_pwr_dwn
errata_report_shim cortex_a75
/* ---------------------------------------------
* This function provides cortex_a75 specific
* register information for crash reporting.

4
lib/cpus/aarch64/cortex_a76.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -511,8 +511,6 @@ func cortex_a76_core_pwr_dwn
ret
endfunc cortex_a76_core_pwr_dwn
errata_report_shim cortex_a76
/* ---------------------------------------------
* This function provides cortex_a76 specific
* register information for crash reporting.

4
lib/cpus/aarch64/cortex_a76ae.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -41,8 +41,6 @@ workaround_reset_end cortex_a76ae, CVE(2022, 23960)
cpu_reset_func_start cortex_a76ae
cpu_reset_func_end cortex_a76ae
errata_report_shim cortex_a76ae
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------

3
lib/cpus/aarch64/cortex_a77.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -167,7 +167,6 @@ func cortex_a77_core_pwr_dwn
ret
endfunc cortex_a77_core_pwr_dwn
errata_report_shim cortex_a77
/* ---------------------------------------------
* This function provides Cortex-A77 specific
* register information for crash reporting.

4
lib/cpus/aarch64/cortex_a78.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -198,8 +198,6 @@ func cortex_a78_core_pwr_dwn
ret
endfunc cortex_a78_core_pwr_dwn
errata_report_shim cortex_a78
/* ---------------------------------------------
* This function provides cortex_a78 specific
* register information for crash reporting.

4
lib/cpus/aarch64/cortex_a78_ae.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
* Copyright (c) 2021-2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -128,8 +128,6 @@ func cortex_a78_ae_core_pwr_dwn
ret
endfunc cortex_a78_ae_core_pwr_dwn
errata_report_shim cortex_a78_ae
/* -------------------------------------------------------
* This function provides cortex_a78_ae specific
* register information for crash reporting.

2
lib/cpus/aarch64/cortex_a78c.S
View file

@ -121,8 +121,6 @@ workaround_reset_end cortex_a78c, CVE(2022, 23960)
cpu_reset_func_start cortex_a78c
cpu_reset_func_end cortex_a78c
errata_report_shim cortex_a78c
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------

2
lib/cpus/aarch64/cortex_gelas.S
View file

@ -58,8 +58,6 @@ func cortex_gelas_core_pwr_dwn
ret
endfunc cortex_gelas_core_pwr_dwn
errata_report_shim cortex_gelas
/* ---------------------------------------------
* This function provides Gelas specific
* register information for crash reporting.

2
lib/cpus/aarch64/cortex_x1.S
View file

@ -66,8 +66,6 @@ func cortex_x1_core_pwr_dwn
ret
endfunc cortex_x1_core_pwr_dwn
errata_report_shim cortex_x1
/* ---------------------------------------------
* This function provides Cortex X1 specific
* register information for crash reporting.

4
lib/cpus/aarch64/cortex_x2.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -182,8 +182,6 @@ func cortex_x2_core_pwr_dwn
ret
endfunc cortex_x2_core_pwr_dwn
errata_report_shim cortex_x2
cpu_reset_func_start cortex_x2
/* Disable speculative loads */
msr SSBS, xzr

2
lib/cpus/aarch64/cortex_x3.S
View file

@ -125,8 +125,6 @@ func cortex_x3_core_pwr_dwn
ret
endfunc cortex_x3_core_pwr_dwn
errata_report_shim cortex_x3
/* ---------------------------------------------
* This function provides Cortex-X3-
* specific register information for crash

2
lib/cpus/aarch64/cortex_x4.S
View file

@ -103,8 +103,6 @@ func cortex_x4_core_pwr_dwn
ret
endfunc cortex_x4_core_pwr_dwn
errata_report_shim cortex_x4
/* ---------------------------------------------
* This function provides Cortex X4-specific
* register information for crash reporting.

2
lib/cpus/aarch64/cortex_x925.S
View file

@ -40,8 +40,6 @@ func cortex_x925_core_pwr_dwn
ret
endfunc cortex_x925_core_pwr_dwn
errata_report_shim cortex_x925
/* ---------------------------------------------
* This function provides Cortex-X925 specific
* register information for crash reporting.

4
lib/cpus/aarch64/denver.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -296,8 +296,6 @@ func denver_cluster_pwr_dwn
ret
endfunc denver_cluster_pwr_dwn
errata_report_shim denver
/* ---------------------------------------------
* This function provides Denver specific
* register information for crash reporting.

3
lib/cpus/aarch64/generic.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, Arm Limited. All rights reserved.
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -79,7 +79,6 @@ endfunc generic_cluster_pwr_dwn
* Unimplemented functions.
* ---------------------------------------------
*/
.equ generic_errata_report, 0
.equ generic_cpu_reg_dump, 0
.equ generic_reset_func, 0

4
lib/cpus/aarch64/neoverse_e1.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -42,8 +42,6 @@ func neoverse_e1_cpu_pwr_dwn
ret
endfunc neoverse_e1_cpu_pwr_dwn
errata_report_shim neoverse_e1
.section .rodata.neoverse_e1_regs, "aS"
neoverse_e1_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""

4
lib/cpus/aarch64/neoverse_n1.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -242,8 +242,6 @@ func neoverse_n1_core_pwr_dwn
ret
endfunc neoverse_n1_core_pwr_dwn
errata_report_shim neoverse_n1
/*
* Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
* inner-shareable invalidation to an arbitrary address followed by a DSB.

4
lib/cpus/aarch64/neoverse_n2.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2023, Arm Limited. All rights reserved.
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -282,8 +282,6 @@ func neoverse_n2_core_pwr_dwn
ret
endfunc neoverse_n2_core_pwr_dwn
errata_report_shim neoverse_n2
/* ---------------------------------------------
* This function provides Neoverse N2 specific
* register information for crash reporting.

2
lib/cpus/aarch64/neoverse_n3.S
View file

@ -45,8 +45,6 @@ func neoverse_n3_core_pwr_dwn
ret
endfunc neoverse_n3_core_pwr_dwn
errata_report_shim neoverse_n3
/* ---------------------------------------------
* This function provides Neoverse-N3 specific
* register information for crash reporting.

4
lib/cpus/aarch64/neoverse_v1.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -259,8 +259,6 @@ func neoverse_v1_core_pwr_dwn
ret
endfunc neoverse_v1_core_pwr_dwn
errata_report_shim neoverse_v1
cpu_reset_func_start neoverse_v1
/* Disable speculative loads */
msr SSBS, xzr

3
lib/cpus/aarch64/neoverse_v2.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -116,7 +116,6 @@ cpu_reset_func_start neoverse_v2
#endif
cpu_reset_func_end neoverse_v2
errata_report_shim neoverse_v2
/* ---------------------------------------------
* This function provides Neoverse V2-
* specific register information for crash

2
lib/cpus/aarch64/neoverse_v3.S
View file

@ -60,8 +60,6 @@ cpu_reset_func_start neoverse_v3
msr SSBS, xzr
cpu_reset_func_end neoverse_v3
errata_report_shim neoverse_v3
/* ---------------------------------------------
* This function provides Neoverse V3 specific
* register information for crash reporting.

4
lib/cpus/aarch64/nevis.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, Arm Limited. All rights reserved.
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -40,8 +40,6 @@ func nevis_core_pwr_dwn
ret
endfunc nevis_core_pwr_dwn
errata_report_shim nevis
.section .rodata.nevis_regs, "aS"
nevis_regs: /* The ASCII list of register names to be reported */
.asciz "cpuectlr_el1", ""

4
lib/cpus/aarch64/qemu_max.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -47,8 +47,6 @@ func qemu_max_cluster_pwr_dwn
b dcsw_op_all
endfunc qemu_max_cluster_pwr_dwn
errata_report_shim qemu_max
/* ---------------------------------------------
* This function provides cpu specific
* register information for crash reporting.

4
lib/cpus/aarch64/rainier.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2023, Arm Limited. All rights reserved.
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -80,8 +80,6 @@ func rainier_core_pwr_dwn
ret
endfunc rainier_core_pwr_dwn
errata_report_shim rainier
/* ---------------------------------------------
* This function provides Rainier specific
* register information for crash reporting.

2
lib/cpus/aarch64/travis.S
View file

@ -54,8 +54,6 @@ func travis_core_pwr_dwn
ret
endfunc travis_core_pwr_dwn
errata_report_shim travis
.section .rodata.travis_regs, "aS"
travis_regs: /* The ASCII list of register names to be reported */
.asciz "cpuectlr_el1", ""

62
lib/cpus/errata_report.c
View file

@ -67,7 +67,7 @@ void print_errata_status(void) {}
* save space. This functionality is only useful on development and platform
* bringup builds, when FEATURE_DETECTION should be used anyway
*/
void __unused generic_errata_report(void)
void generic_errata_report(void)
{
struct cpu_ops *cpu_ops = get_cpu_ops_ptr();
struct erratum_entry *entry = cpu_ops->errata_list_start;
@ -159,70 +159,16 @@ static __unused int errata_needs_reporting(spinlock_t *lock, uint32_t *reported)
*/
void print_errata_status(void)
{
struct cpu_ops *cpu_ops;
#ifdef IMAGE_BL1
/*
* BL1 doesn't have per-CPU data. So retrieve the CPU operations
* directly.
*/
cpu_ops = get_cpu_ops_ptr();
if (cpu_ops->errata_func != NULL) {
cpu_ops->errata_func();
}
generic_errata_report();
#else /* IMAGE_BL1 */
cpu_ops = (void *) get_cpu_data(cpu_ops_ptr);
struct cpu_ops *cpu_ops = (void *) get_cpu_data(cpu_ops_ptr);
assert(cpu_ops != NULL);
if (cpu_ops->errata_func == NULL) {
return;
}
if (errata_needs_reporting(cpu_ops->errata_lock, cpu_ops->errata_reported)) {
cpu_ops->errata_func();
generic_errata_report();
}
#endif /* IMAGE_BL1 */
}
/*
* Old errata status message printer
* TODO: remove once all cpus have been converted to the new printing method
*/
void __unused errata_print_msg(unsigned int status, const char *cpu, const char *id)
{
/* Errata status strings */
static const char *const errata_status_str[] = {
[ERRATA_NOT_APPLIES] = "not applied",
[ERRATA_APPLIES] = "applied",
[ERRATA_MISSING] = "missing!"
};
static const char *const __unused bl_str = BL_STRING;
const char *msg __unused;
assert(status < ARRAY_SIZE(errata_status_str));
assert(cpu != NULL);
assert(id != NULL);
msg = errata_status_str[status];
switch (status) {
case ERRATA_NOT_APPLIES:
VERBOSE(ERRATA_FORMAT, bl_str, cpu, id, msg);
break;
case ERRATA_APPLIES:
INFO(ERRATA_FORMAT, bl_str, cpu, id, msg);
break;
case ERRATA_MISSING:
WARN(ERRATA_FORMAT, bl_str, cpu, id, msg);
break;
default:
WARN(ERRATA_FORMAT, bl_str, cpu, id, "unknown");
break;
}
}
#endif /* !REPORT_ERRATA */

12
plat/qti/common/src/aarch64/qti_kryo4_gold.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -41,16 +41,6 @@ func qti_kryo4_gold_cluster_pwr_dwn
ret
endfunc qti_kryo4_gold_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Kryo4 Gold. Must follow AAPCS.
*/
func qti_kryo4_gold_errata_report
/* TODO : Need to add support. Required only for debug bl31 image.*/
ret
endfunc qti_kryo4_gold_errata_report
#endif
/* ---------------------------------------------
* This function provides kryo4_gold specific
* register information for crash reporting.

13
plat/qti/common/src/aarch64/qti_kryo4_silver.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -35,17 +35,6 @@ func qti_kryo4_silver_cluster_pwr_dwn
ret
endfunc qti_kryo4_silver_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Kryo4 Silver. Must follow AAPCS.
*/
func qti_kryo4_silver_errata_report
/* TODO : Need to add support. Required only for debug bl31 image.*/
ret
endfunc qti_kryo4_silver_errata_report
#endif
/* ---------------------------------------------
* This function provides kryo4_silver specific
* register information for crash reporting.

12
plat/qti/common/src/aarch64/qti_kryo6_gold.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -41,16 +41,6 @@ func qti_kryo6_gold_cluster_pwr_dwn
ret
endfunc qti_kryo6_gold_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Kryo4 Gold. Must follow AAPCS.
*/
func qti_kryo6_gold_errata_report
/* TODO : Need to add support. Required only for debug bl31 image.*/
ret
endfunc qti_kryo6_gold_errata_report
#endif
/* ---------------------------------------------
* This function provides kryo4_gold specific
* register information for crash reporting.

13
plat/qti/common/src/aarch64/qti_kryo6_silver.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -35,17 +35,6 @@ func qti_kryo6_silver_cluster_pwr_dwn
ret
endfunc qti_kryo6_silver_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Kryo4 Silver. Must follow AAPCS.
*/
func qti_kryo6_silver_errata_report
/* TODO : Need to add support. Required only for debug bl31 image.*/
ret
endfunc qti_kryo6_silver_errata_report
#endif
/* ---------------------------------------------
* This function provides kryo4_silver specific
* register information for crash reporting.