This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned type.
Appended "u" suffix to integer constant to represent it as
unsigned type.
Change-Id: I08b055134d6bd0380cca1e5b6ee527d6045a76c5
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned type.
Appended "U" suffix to integer constant to represent it as
unsigned type.
Change-Id: I76f3c5903ed21ecba4d600e879d93026fc744f6c
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.
Change-Id: I546cf47edc6332ee193b4771c88ae30553687f19
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.
Change-Id: I8de33e774178720411313021a7b157045d3cefa0
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.
Change-Id: I8941f3c713586c36396e1f3731b99ffadc28c6e8
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
* changes:
fix(versal2): typecast operands to match data type
fix(versal): typecast operands to match data type
fix(versal-net): typecast operands to match data type
fix(xilinx): typecast operands to match data type
fix(zynqmp): typecast operands to match data type
fix(versal-net): typecast operands to match data type
fix(versal): typecast operands to match data type
fix(xilinx): typecast operands to match data type
fix(zynqmp): typecast operands to match data type
fix(versal2): typecast expressions to match data type
fix(versal-net): typecast expressions to match data type
fix(versal): typecast expressions to match data type
fix(xilinx): typecast expressions to match data type
fix(zynqmp): typecast expressions to match data type
fix(zynqmp): align essential type categories
fix(zynqmp): typecast expression to match data type
fix(xilinx): typecast expression to match data type
Commit a6485b2 ("refactor(delay-timer): add timer callback
functions") introduced a requirement for timer-related APIs
to have a timer object initialized before use. This caused
assertion failures in SMMU routines on Neoverse platforms,
as they relied on timer APIs.
Resolve this issue by initializing the timer early during
platform boot to set up the timer_ops object properly.
Change-Id: I3d9ababdb7897185f23e9ccf982b9aab6c666b8c
Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I37ec9f8d716347df9acea5eb084f5a423a32a058
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: Ie82297e7eb5faa5d45b1a613c59516052e0c5ecb
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: Ie2d32d5554d251cde8a9c8b7c7a85666ea505a15
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I1606422aadfd64b283fd9948b6dadcddecdf61e0
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I141fbc554265173df0ca90c2ddc7f28137c6b0f1
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: If0a6ffa84c4d1ce5ae08337a4eb20c9a221d7795
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I41b08349fc6023458ffc6e126f58293a9ef37422
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I675f1b2ac408b70a9ca307fb5161ebb8e597897c
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I016f9df3811d80cd230257b5533d4d15a15fe14f
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: Ia352e3cf261b52777c1c431701e1e6c3be9cd279
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I5add78285ff0e48aa6c0fb639e7e2924f5bf9000
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: Ide520aa8ec900d0e23e80753d7082e34b6897e8f
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic conversions
are performed shall have the same essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I9110ea86f5ee49af0b21be78fd0890742ef95ddf
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic conversions
are performed shall have the same essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I847af07f5e4f139384c1ed50bee765b892a6e9cd
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.7:
If a composite expression is used as one operand of an operator in
which the usual arithmetic conversions are performed then the other
operand shall not have wider essential type.
Explicitly type casted to match the data type of both the operands.
Change-Id: I670304682cc4945b8575f125ac750d0dc69079a7
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.6:
The value of a composite expression shall not be assigned to
an object with wider essential type.
Explicitly type casted to match the data type of composite
expression.
Change-Id: I6497453f9f7455ae2f1ad8a18760ff0ef41d7c40
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.6:
The value of a composite expression shall not be assigned to an
object with wider essential type.
Explicitly type casted to match the data type of composite
expression.
Change-Id: I0fd845496b4d6ac702027eb2075a23b15849f7d6
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure access to pmu counters on TC4
feat(tc): define MCN related macros for TC4
The name field of console_info structure was missed in
checksum calculation. This is corrected by adding a new
helper checksum_calc() which computes the checksum in a
field agnostic manner.
Change-Id: I98d35d53e1faccf1221e8eddb122558ae359a2d5
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I1a85ba646604336ce3f16c28171589af78f65251
Add 'kaslr-seed' node in device tree for TC3.
Note, TC4 doesn't need to add this node as it can dynamically generate
seed based on CPU arch's RNG_TRAP feature.
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I5c3f857d0f4e81ccd3bacb4c1ab032c8ea6e6873
MCN PMU counters are by default non-accesible from non-secure world,
so enable the non-secure access to those PMU counters so that linux
perf driver can read them.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I1cf1f88f97e9062592fd5603a78fd36f15a15f89
Define MCN related macros for TC4 to add TC4 specific MCN PMU
nodes in dts and to enable MCN PMU NS access in further commits.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ifc02fcd833888a9953fac404585468316aa0168c
Add APU SMMU hardware semaphore operations to make APU SMMU
able to sync the power status.
Change-Id: I1926cab990fba54a2ea694ac6d9e87135dfb19cf
Signed-off-by: Karl Li <karl.li@mediatek.com>
1. Add smpu protection for APU secure memory.
2. Move emi mpu protection for mt8188 to platform folder
Since the smpu driver has not upstream, we currently leave the interface
and do nothing until smpu driver is ready.
Change-Id: Id70162e90a7deb64befe90f09a841a0903535482
Signed-off-by: Karl Li <karl.li@mediatek.com>
APU RCX is a sub-domain in apusys, connecting several APU components.
The APU RCX DevAPC control lives in APU and can only be set after
APU is powered on.
The APUSYS kernel driver will trigger RCX DevAPC init by smc call.
Change-Id: I3a9b014ea1be7ee80fd6861ad088f1dec5410872
Signed-off-by: Karl Li <karl.li@mediatek.com>
Add APU kernel control operations to provide the bootup init functions.
1. Add software workaround for certain operations on mt8196.
2. Add APU logger operations.
3. Add function to clear mbox spare register, which is used in APU
booting process.
4. Add function to setup CE binary to make sure the CE binary version
is align with the APU firmware.
Change-Id: Ic99adba1409c020c72179ea135e0d4291fc3f384
Signed-off-by: Karl Li <karl.li@mediatek.com>
1. Add APU power on/off functions
2. Refine the APU power on/off interface for mt8188
3. Add dcm setup function to support mt8196
Change-Id: Ie1caca40f89de71caac037fabe7e7455ff2a1872
Signed-off-by: Karl Li <karl.li@mediatek.com>
APUMMU is the MMU in APU, which is responsible for inner address
mapping. The APU kernel driver will setup the APUMMU by SMC call.
Change-Id: Iad7532883e42c288aeb0d23ab419f4dc6d8630f2
Signed-off-by: Karl Li <karl.li@mediatek.com>
Enable mt8196 apusys mailbox mpu protection and
move the mt8188 setting to platform folder
Change-Id: I76b68318bb88e56b12cdacd9e2b998699ca6b48e
Signed-off-by: Karl Li <karl.li@mediatek.com>
Remap the request from domain 5, 7, 14 to domain 6 and setup security
sideband
Change-Id: I06d377f4bcc542bf22e0a04ffb45cf52b7528a75
Signed-off-by: Karl Li <karl.li@mediatek.com>
Apusys AO DevAPC is a set of control registers inside APU, controlling
the access permission of APU AO (Always On) domain.
This patch add the mt8196 APU AO DevAPC setting to setup the protection.
Change-Id: I975a92795031cd1813442302890e29b671ef16f1
Signed-off-by: Karl Li <karl.li@mediatek.com>
Add the APU (AI processing unit) power init flow to prepare the hardware
setting before using APU power functions.
Change-Id: I595b1d5100a4f083263de6527f920e5168700b7a
Signed-off-by: Karl Li <karl.li@mediatek.com>
* changes:
fix(cpus): workaround for CVE-2024-5660 for Cortex-X925
fix(cpus): workaround for CVE-2024-5660 for Cortex-X2
fix(cpus): workaround for CVE-2024-5660 for Cortex-A77
fix(cpus): workaround for CVE-2024-5660 for Neoverse-V1
fix(cpus): workaround for CVE-2024-5660 for Cortex-A78_AE
fix(cpus): workaround for CVE-2024-5660 for Cortex-A78C
fix(cpus): workaround for CVE-2024-5660 for Cortex-A78
fix(cpus): workaround for CVE-2024-5660 for Cortex-X1
fix(cpus): workaround for CVE-2024-5660 for Neoverse-N2
fix(cpus): workaround for CVE-2024-5660 for Cortex-A710
fix(cpus): workaround for CVE-2024-5660 for Neoverse-V2
fix(cpus): workaround for CVE-2024-5660 for Cortex-X3
fix(cpus): workaround for CVE-2024-5660 for Neoverse-V3
fix(cpus): workaround for CVE-2024-5660 for Cortex-X4
