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fix(versal): add unsigned suffix to match data type

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This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned type.
Appended "U" suffix to integer constant to represent it as
unsigned type.

Change-Id: I76f3c5903ed21ecba4d600e879d93026fc744f6c
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This commit is contained in:
Maheedhar Bollapalli 2024-10-25 03:53:56 +00:00
parent 9f51da5e2e
commit 4b2324042a
1 changed files with 10 additions and 10 deletions
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20
plat/xilinx/versal/include/versal_def.h
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@ -49,10 +49,10 @@
/*******************************************************************************
* memory map related constants
******************************************************************************/
#define DEVICE0_BASE 0xFF000000
#define DEVICE0_SIZE 0x00E00000
#define DEVICE1_BASE 0xF9000000
#define DEVICE1_SIZE 0x00800000
#define DEVICE0_BASE U(0xFF000000)
#define DEVICE0_SIZE U(0x00E00000)
#define DEVICE1_BASE U(0xF9000000)
#define DEVICE1_SIZE U(0x00800000)
/*******************************************************************************
* IRQ constants
@ -63,16 +63,16 @@
/*******************************************************************************
* CCI-400 related constants
******************************************************************************/
#define PLAT_ARM_CCI_BASE 0xFD000000
#define PLAT_ARM_CCI_SIZE 0x00100000
#define PLAT_ARM_CCI_BASE U(0xFD000000)
#define PLAT_ARM_CCI_SIZE U(0x00100000)
#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
/*******************************************************************************
* UART related constants
******************************************************************************/
#define VERSAL_UART0_BASE 0xFF000000
#define VERSAL_UART1_BASE 0xFF010000
#define VERSAL_UART0_BASE U(0xFF000000)
#define VERSAL_UART1_BASE U(0xFF010000)
#if CONSOLE_IS(pl011) || CONSOLE_IS(dtb)
# define UART_BASE VERSAL_UART0_BASE
@ -115,8 +115,8 @@
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
#define CRF_BASE 0xFD1A0000
#define CRF_SIZE 0x00600000
#define CRF_BASE U(0xFD1A0000)
#define CRF_SIZE U(0x00600000)
/* CRF registers and bitfields */
#define CRF_RST_APU (CRF_BASE + 0X00000300)