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https://github.com/ARM-software/arm-trusted-firmware.git
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Merge changes from topic "bk/smccc_feature" into integration
* changes: fix(trbe): add a tsb before context switching fix(spe): add a psb before updating context and remove context saving
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
b41b9997ca
6 changed files with 21 additions and 136 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -224,13 +224,6 @@
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.space SPINLOCK_ASM_SIZE
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.endm
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/*
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* With RAS extension executes esb instruction, else NOP
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*/
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.macro esb
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.inst 0xd503221f
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.endm
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/*
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* Helper macro to read system register value into x0
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*/
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@ -265,6 +258,14 @@
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msr SYSREG_SB, xzr
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.endm
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.macro psb_csync
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hint #17 /* use the hint synonym for compatibility */
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.endm
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.macro tsb_csync
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hint #18 /* use the hint synonym for compatibility */
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.endm
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/*
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* Macro for using speculation barrier instruction introduced by
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* FEAT_SB, if it's enabled.
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@ -14,7 +14,6 @@
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void spe_enable(cpu_context_t *ctx);
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void spe_disable(cpu_context_t *ctx);
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void spe_init_el2_unused(void);
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void spe_stop(void);
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#else
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static inline void spe_enable(cpu_context_t *ctx)
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{
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@ -25,9 +24,6 @@ static inline void spe_disable(cpu_context_t *ctx)
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static inline void spe_init_el2_unused(void)
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{
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}
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static inline void spe_stop(void)
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{
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}
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#endif /* ENABLE_SPE_FOR_NS */
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#endif /* SPE_H */
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@ -400,7 +400,6 @@ no_mpam:
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/* PMUv3 is presumed to be always present */
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mrs x9, pmcr_el0
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str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
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isb
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#if CTX_INCLUDE_PAUTH_REGS
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/* ----------------------------------------------------------
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* Save the ARMv8.3-PAuth keys as they are not banked
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@ -440,6 +439,18 @@ no_mpam:
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* -----------------------------------------------------------------
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*/
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func prepare_el3_entry
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/*
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* context is about to mutate, so make sure we don't affect any still
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* in-flight profiling operations. We don't care that they actually
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* finish, that can still be later. NOP if not present
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*/
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#if ENABLE_SPE_FOR_NS
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psb_csync
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#endif
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#if ENABLE_TRBE_FOR_NS
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tsb_csync
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#endif
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isb
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save_gp_pmcr_pauth_regs
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setup_el3_execution_context
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ret
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@ -9,26 +9,10 @@
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/extensions/spe.h>
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#include <plat/common/platform.h>
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typedef struct spe_ctx {
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u_register_t pmblimitr_el1;
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} spe_ctx_t;
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static struct spe_ctx spe_ctxs[PLATFORM_CORE_COUNT];
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static inline void psb_csync(void)
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{
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/*
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* The assembler does not yet understand the psb csync mnemonic
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* so use the equivalent hint instruction.
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*/
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__asm__ volatile("hint #17");
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}
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void spe_enable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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@ -90,63 +74,3 @@ void spe_init_el2_unused(void)
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v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1);
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write_mdcr_el2(v);
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}
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void spe_stop(void)
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{
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uint64_t v;
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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/* Disable profiling buffer */
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v = read_pmblimitr_el1();
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v &= ~(1ULL << 0);
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write_pmblimitr_el1(v);
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isb();
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}
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static void *spe_drain_buffers_hook(const void *arg)
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{
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if (!is_feat_spe_supported())
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return (void *)-1;
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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return (void *)0;
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}
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static void *spe_context_save(const void *arg)
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{
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unsigned int core_pos;
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struct spe_ctx *ctx;
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if (is_feat_spe_supported()) {
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core_pos = plat_my_core_pos();
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ctx = &spe_ctxs[core_pos];
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ctx->pmblimitr_el1 = read_pmblimitr_el1();
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}
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return NULL;
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}
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static void *spe_context_restore(const void *arg)
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{
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unsigned int core_pos;
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struct spe_ctx *ctx;
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if (is_feat_spe_supported()) {
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core_pos = plat_my_core_pos();
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ctx = &spe_ctxs[core_pos];
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write_pmblimitr_el1(ctx->pmblimitr_el1);
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}
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return NULL;
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}
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SUBSCRIBE_TO_EVENT(cm_entering_secure_world, spe_drain_buffers_hook);
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, spe_context_save);
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, spe_context_restore);
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@ -7,18 +7,8 @@
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/extensions/trbe.h>
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static void tsb_csync(void)
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{
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/*
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* The assembler does not yet understand the tsb csync mnemonic
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* so use the equivalent hint instruction.
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*/
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__asm__ volatile("hint #18");
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}
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void trbe_enable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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@ -68,21 +58,3 @@ void trbe_init_el2_unused(void)
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*/
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write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
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}
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static void *trbe_drain_trace_buffers_hook(const void *arg __unused)
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{
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if (is_feat_trbe_supported()) {
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/*
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* Before switching from normal world to secure world
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* the trace buffers need to be drained out to memory. This is
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* required to avoid an invalid memory access when TTBR is switched
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* for entry to S-EL1.
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*/
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tsb_csync();
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dsbnsh();
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}
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return (void *)0;
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}
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SUBSCRIBE_TO_EVENT(cm_entering_secure_world, trbe_drain_trace_buffers_hook);
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@ -1169,8 +1169,6 @@ int psci_secondaries_brought_up(void)
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******************************************************************************/
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void psci_pwrdown_cpu(unsigned int power_level)
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{
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psci_do_manage_extensions();
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#if HW_ASSISTED_COHERENCY
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/*
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* With hardware-assisted coherency, the CPU drivers only initiate the
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@ -1290,20 +1288,3 @@ bool psci_are_all_cpus_on_safe(void)
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return true;
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}
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/*******************************************************************************
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* This function performs architectural feature specific management.
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* It ensures the architectural features are disabled during cpu
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* power off/suspend operations.
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******************************************************************************/
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void psci_do_manage_extensions(void)
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{
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/*
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* On power down we need to disable statistical profiling extensions
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* before exiting coherency.
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*/
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if (is_feat_spe_supported()) {
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spe_stop();
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}
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}
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