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73d98e3759
Just like for SPE, we need to synchronize TRBE samples before we change the context to ensure everything goes where it was intended to. If that is not done, the in-flight entries might use any piece of now incorrect context as there are no implicit ordering requirements. Prior to root context, the buffer drain hooks would have done that. But now that must happen much earlier. So add a tsb to prepare_el3_entry as well. Annoyingly, the barrier can be reordered relative to other instructions by default (rule RCKVWP). So add an isb after the psb/tsb to assure that they are ordered, at least as far as context is concerned. Then, drop the buffer draining hooks. Everything they need to do is already done by now. There's a notable difference in that there are no dsb-s now. Since EL3 does not access the buffers or the feature specific context, we don't need to wait for them to finish. Finally, drop a stray isb in the context saving macro. It is now absorbed into root context, but was missed. Change-Id: I30797a40ac7f91d0bb71ad271a1597e85092ccd5 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/*
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/extensions/trbe.h>
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void trbe_enable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.NSTBE = 0b0
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* Trace Buffer owning Security state is Non-secure state. If FEAT_RME
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* is not implemented, this field is RES0.
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*
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* MDCR_EL3.NSTB = 0b11
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* Allow access of trace buffer control registers from NS-EL1 and
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* NS-EL2, tracing is prohibited in Secure and Realm state (if
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* implemented).
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*/
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mdcr_el3_val |= MDCR_NSTB(MDCR_NSTB_EL1);
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mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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void trbe_disable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.NSTBE = 0b0
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* Trace Buffer owning Security state is secure state. If FEAT_RME
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* is not implemented, this field is RES0.
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*
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* MDCR_EL3.NSTB = 0b00
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* Clear these bits to disable access of trace buffer control registers
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* from lower ELs in any security state.
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*/
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mdcr_el3_val &= ~(MDCR_NSTB(MDCR_NSTB_EL1));
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mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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void trbe_init_el2_unused(void)
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{
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/*
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* MDCR_EL2.E2TB: Set to zero so that the trace Buffer
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* owning exception level is NS-EL1 and, tracing is
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* prohibited at NS-EL2. These bits are RES0 when
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* FEAT_TRBE is not implemented.
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*/
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write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
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}
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