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https://github.com/ARM-software/arm-trusted-firmware.git
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73d98e3759
Just like for SPE, we need to synchronize TRBE samples before we change the context to ensure everything goes where it was intended to. If that is not done, the in-flight entries might use any piece of now incorrect context as there are no implicit ordering requirements. Prior to root context, the buffer drain hooks would have done that. But now that must happen much earlier. So add a tsb to prepare_el3_entry as well. Annoyingly, the barrier can be reordered relative to other instructions by default (rule RCKVWP). So add an isb after the psb/tsb to assure that they are ordered, at least as far as context is concerned. Then, drop the buffer draining hooks. Everything they need to do is already done by now. There's a notable difference in that there are no dsb-s now. Since EL3 does not access the buffers or the feature specific context, we don't need to wait for them to finish. Finally, drop a stray isb in the context saving macro. It is now absorbed into root context, but was missed. Change-Id: I30797a40ac7f91d0bb71ad271a1597e85092ccd5 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
329 lines
8.4 KiB
ArmAsm
329 lines
8.4 KiB
ArmAsm
/*
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* Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ASM_MACROS_S
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#define ASM_MACROS_S
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#include <arch.h>
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#include <common/asm_macros_common.S>
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#include <lib/spinlock.h>
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/*
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* TLBI instruction with type specifier that implements the workaround for
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* errata 813419 of Cortex-A57 or errata 1286807 of Cortex-A76.
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*/
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#if ERRATA_A57_813419 || ERRATA_A76_1286807
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#define TLB_INVALIDATE(_type) \
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tlbi _type; \
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dsb ish; \
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tlbi _type
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#else
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#define TLB_INVALIDATE(_type) \
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tlbi _type
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#endif
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/*
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* Create a stack frame at the start of an assembly function. Will also
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* add all necessary call frame information (cfi) directives for a
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* pretty stack trace. This is necessary as there is quite a bit of
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* flexibility within a stack frame and the stack pointer can move
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* around throughout the function. If the debugger isn't told where to
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* find things, it gets lost, gives up and displays nothing. So inform
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* the debugger of what's where. Anchor the Canonical Frame Address
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* (CFA; the thing used to track what's where) to the frame pointer as
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* that's not expected to change in the function body and no extra
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* bookkeeping will be necessary, allowing free movement of the sp
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*
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* _frame_size: requested space for caller to use. Must be a mutliple
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* of 16 for stack pointer alignment
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*/
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.macro func_prologue _frame_size=0
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.if \_frame_size & 0xf
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.error "frame_size must have stack pointer alignment (multiple of 16)"
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.endif
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/* put frame record at top of frame */
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stp x29, x30, [sp, #-0x10]!
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mov x29,sp
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.if \_frame_size
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sub sp, sp, #\_frame_size
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.endif
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/* point CFA to start of frame record, i.e. x29 + 0x10 */
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.cfi_def_cfa x29, 0x10
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/* inform it about x29, x30 locations */
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.cfi_offset x30, -0x8
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.cfi_offset x29, -0x10
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.endm
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/*
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* Clear stack frame at the end of an assembly function.
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*
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* _frame_size: the value passed to func_prologue
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*/
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.macro func_epilogue _frame_size=0
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/* remove requested space */
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.if \_frame_size
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add sp, sp, #\_frame_size
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.endif
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ldp x29, x30, [sp], #0x10
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.endm
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.macro dcache_line_size reg, tmp
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mrs \tmp, ctr_el0
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ubfx \tmp, \tmp, #16, #4
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mov \reg, #4
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lsl \reg, \reg, \tmp
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.endm
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.macro icache_line_size reg, tmp
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mrs \tmp, ctr_el0
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and \tmp, \tmp, #0xf
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mov \reg, #4
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lsl \reg, \reg, \tmp
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.endm
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.macro smc_check label
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mrs x0, esr_el3
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ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x0, #EC_AARCH64_SMC
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b.ne $label
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.endm
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/*
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* Declare the exception vector table, enforcing it is aligned on a
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* 2KB boundary, as required by the ARMv8 architecture.
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* Use zero bytes as the fill value to be stored in the padding bytes
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* so that it inserts illegal AArch64 instructions. This increases
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* security, robustness and potentially facilitates debugging.
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*/
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.macro vector_base label, section_name=.vectors
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.section \section_name, "ax"
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.align 11, 0
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\label:
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.endm
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/*
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* Create an entry in the exception vector table, enforcing it is
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* aligned on a 128-byte boundary, as required by the ARMv8 architecture.
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* Use zero bytes as the fill value to be stored in the padding bytes
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* so that it inserts illegal AArch64 instructions. This increases
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* security, robustness and potentially facilitates debugging.
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*/
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.macro vector_entry label, section_name=.vectors
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.cfi_sections .debug_frame
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.section \section_name, "ax"
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.align 7, 0
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.type \label, %function
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.cfi_startproc
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\label:
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.endm
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/*
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* Add the bytes until fill the full exception vector, whose size is always
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* 32 instructions. If there are more than 32 instructions in the
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* exception vector then an error is emitted.
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*/
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.macro end_vector_entry label
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.cfi_endproc
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.fill \label + (32 * 4) - .
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.endm
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/*
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* This macro calculates the base address of the current CPU's MP stack
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* using the plat_my_core_pos() index, the name of the stack storage
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* and the size of each stack
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* Out: X0 = physical address of stack base
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* Clobber: X30, X1, X2
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*/
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.macro get_my_mp_stack _name, _size
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bl plat_my_core_pos
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adrp x2, (\_name + \_size)
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add x2, x2, :lo12:(\_name + \_size)
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mov x1, #\_size
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madd x0, x0, x1, x2
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.endm
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/*
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* This macro calculates the base address of a UP stack using the
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* name of the stack storage and the size of the stack
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* Out: X0 = physical address of stack base
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*/
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.macro get_up_stack _name, _size
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adrp x0, (\_name + \_size)
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add x0, x0, :lo12:(\_name + \_size)
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.endm
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/*
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* Helper macro to generate the best mov/movk combinations according
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* the value to be moved. The 16 bits from '_shift' are tested and
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* if not zero, they are moved into '_reg' without affecting
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* other bits.
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*/
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.macro _mov_imm16 _reg, _val, _shift
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.if (\_val >> \_shift) & 0xffff
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.if (\_val & (1 << \_shift - 1))
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movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift
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.else
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mov \_reg, \_val & (0xffff << \_shift)
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.endif
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.endif
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.endm
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/*
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* Helper macro to load arbitrary values into 32 or 64-bit registers
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* which generates the best mov/movk combinations. Many base addresses
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* are 64KB aligned the macro will eliminate updating bits 15:0 in
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* that case
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*/
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.macro mov_imm _reg, _val
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.if (\_val) == 0
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mov \_reg, #0
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.else
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_mov_imm16 \_reg, (\_val), 0
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_mov_imm16 \_reg, (\_val), 16
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_mov_imm16 \_reg, (\_val), 32
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_mov_imm16 \_reg, (\_val), 48
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.endif
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.endm
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/*
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* Macro to mark instances where we're jumping to a function and don't
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* expect a return. To provide the function being jumped to with
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* additional information, we use 'bl' instruction to jump rather than
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* 'b'.
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*
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* Debuggers infer the location of a call from where LR points to, which
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* is usually the instruction after 'bl'. If this macro expansion
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* happens to be the last location in a function, that'll cause the LR
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* to point a location beyond the function, thereby misleading debugger
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* back trace. We therefore insert a 'nop' after the function call for
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* debug builds, unless 'skip_nop' parameter is non-zero.
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*/
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.macro no_ret _func:req, skip_nop=0
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bl \_func
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#if DEBUG
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.ifeq \skip_nop
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nop
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.endif
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#endif
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.endm
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/*
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* Reserve space for a spin lock in assembly file.
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*/
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.macro define_asm_spinlock _name:req
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.align SPINLOCK_ASM_ALIGN
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\_name:
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.space SPINLOCK_ASM_SIZE
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.endm
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/*
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* Helper macro to read system register value into x0
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*/
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.macro read reg:req
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#if ENABLE_BTI
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bti j
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#endif
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mrs x0, \reg
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ret
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.endm
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/*
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* Helper macro to write value from x1 to system register
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*/
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.macro write reg:req
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#if ENABLE_BTI
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bti j
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#endif
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msr \reg, x1
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ret
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.endm
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/*
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* The "sb" instruction was introduced later into the architecture,
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* so not all toolchains understand it. Some deny its usage unless
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* a supported processor is specified on the build command line.
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* Use sb's system register encoding to work around this, we already
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* guard the sb execution with a feature flag.
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*/
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.macro sb_barrier_insn
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msr SYSREG_SB, xzr
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.endm
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.macro psb_csync
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hint #17 /* use the hint synonym for compatibility */
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.endm
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.macro tsb_csync
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hint #18 /* use the hint synonym for compatibility */
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.endm
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/*
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* Macro for using speculation barrier instruction introduced by
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* FEAT_SB, if it's enabled.
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*/
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.macro speculation_barrier
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#if ENABLE_FEAT_SB
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sb_barrier_insn
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#else
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dsb sy
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isb
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#endif
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.endm
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/*
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* Macro for mitigating against speculative execution beyond ERET. Uses the
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* speculation barrier instruction introduced by FEAT_SB, if it's enabled.
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*/
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.macro exception_return
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eret
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#if ENABLE_FEAT_SB
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sb_barrier_insn
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#else
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dsb nsh
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isb
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#endif
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.endm
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/*
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* Macro to unmask External Aborts by changing PSTATE.A bit.
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* Put explicit synchronization event to ensure newly unmasked interrupt
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* is taken immediately.
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*/
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.macro unmask_async_ea
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msr daifclr, #DAIF_ABT_BIT
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isb
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.endm
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/* Macro for error synchronization on exception boundries.
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* With FEAT_RAS enabled, it is assumed that FEAT_IESB is also present
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* and enabled.
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* FEAT_IESB provides an implicit error synchronization event at exception
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* entry and exception return, so there is no need for any explicit instruction.
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*/
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.macro synchronize_errors
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#if !ENABLE_FEAT_RAS
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/* Complete any stores that may return an abort */
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dsb sy
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/* Synchronise the CPU context with the completion of the dsb */
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isb
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#endif
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.endm
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/*
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* Helper macro to instruction adr <reg>, <symbol> where <symbol> is
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* within the range +/- 4 GB.
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*/
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.macro adr_l, dst, sym
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adrp \dst, \sym
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add \dst, \dst, :lo12:\sym
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.endm
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#endif /* ASM_MACROS_S */
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