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fix(versal2): typecast expressions to match data type

Browse source 
This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Ia352e3cf261b52777c1c431701e1e6c3be9cd279
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This commit is contained in:
Maheedhar Bollapalli 2024-10-21 05:57:58 +00:00
parent 3cbe0ae5b8
commit fbc415d204
6 changed files with 101 additions and 101 deletions
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4
plat/amd/versal2/aarch64/common.c
View file

@ -75,8 +75,8 @@ void board_detection(void)
uint32_t version_type;
version_type = mmio_read_32(PMC_TAP_VERSION);
platform_id = FIELD_GET(PLATFORM_MASK, version_type);
platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version_type);
platform_id = FIELD_GET((uint32_t)PLATFORM_MASK, version_type);
platform_version = FIELD_GET((uint32_t)PLATFORM_VERSION_MASK, version_type);
if (platform_id == QEMU_COSIM) {
platform_id = QEMU;

2
plat/amd/versal2/include/def.h
View file

@ -12,7 +12,7 @@
#include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h>
#define MAX_INTR_EL3 2
#define MAX_INTR_EL3 2U
/* List all consoles */
#define VERSAL2_CONSOLE_ID_none 0

180
plat/amd/versal2/include/versal2-scmi.h
View file

@ -10,96 +10,96 @@
#ifndef _VERSAL2_SCMI_H
#define _VERSAL2_SCMI_H
#define CLK_GEM0_0 0
#define CLK_GEM0_1 1
#define CLK_GEM0_2 2
#define CLK_GEM0_3 3
#define CLK_GEM0_4 4
#define CLK_GEM1_0 5
#define CLK_GEM1_1 6
#define CLK_GEM1_2 7
#define CLK_GEM1_3 8
#define CLK_GEM1_4 9
#define CLK_SERIAL0_0 10
#define CLK_SERIAL0_1 11
#define CLK_SERIAL1_0 12
#define CLK_SERIAL1_1 13
#define CLK_UFS0_0 14
#define CLK_UFS0_1 15
#define CLK_UFS0_2 16
#define CLK_USB0_0 17
#define CLK_USB0_1 18
#define CLK_USB0_2 19
#define CLK_USB1_0 20
#define CLK_USB1_1 21
#define CLK_USB1_2 22
#define CLK_MMC0_0 23
#define CLK_MMC0_1 24
#define CLK_MMC0_2 25
#define CLK_MMC1_0 26
#define CLK_MMC1_1 27
#define CLK_MMC1_2 28
#define CLK_TTC0_0 29
#define CLK_TTC1_0 30
#define CLK_TTC2_0 31
#define CLK_TTC3_0 32
#define CLK_TTC4_0 33
#define CLK_TTC5_0 34
#define CLK_TTC6_0 35
#define CLK_TTC7_0 36
#define CLK_I2C0_0 37
#define CLK_I2C1_0 38
#define CLK_I2C2_0 39
#define CLK_I2C3_0 40
#define CLK_I2C4_0 41
#define CLK_I2C5_0 42
#define CLK_I2C6_0 43
#define CLK_I2C7_0 44
#define CLK_OSPI0_0 45
#define CLK_QSPI0_0 46
#define CLK_QSPI0_1 47
#define CLK_WWDT0_0 48
#define CLK_WWDT1_0 49
#define CLK_WWDT2_0 50
#define CLK_WWDT3_0 51
#define CLK_ADMA0_0 52
#define CLK_ADMA0_1 53
#define CLK_ADMA1_0 54
#define CLK_ADMA1_1 55
#define CLK_ADMA2_0 56
#define CLK_ADMA2_1 57
#define CLK_ADMA3_0 58
#define CLK_ADMA3_1 59
#define CLK_ADMA4_0 60
#define CLK_ADMA4_1 61
#define CLK_ADMA5_0 62
#define CLK_ADMA5_1 63
#define CLK_ADMA6_0 64
#define CLK_ADMA6_1 65
#define CLK_ADMA7_0 66
#define CLK_ADMA7_1 67
#define CLK_CAN0_0 68
#define CLK_CAN0_1 69
#define CLK_CAN1_0 70
#define CLK_CAN1_1 71
#define CLK_CAN2_0 72
#define CLK_CAN2_1 73
#define CLK_CAN3_0 74
#define CLK_CAN3_1 75
#define CLK_PS_GPIO_0 76
#define CLK_PMC_GPIO_0 77
#define CLK_SPI0_0 78
#define CLK_SPI0_1 79
#define CLK_SPI1_0 80
#define CLK_SPI1_1 81
#define CLK_I3C0_0 82
#define CLK_I3C1_0 83
#define CLK_I3C2_0 84
#define CLK_I3C3_0 85
#define CLK_I3C4_0 86
#define CLK_I3C5_0 87
#define CLK_I3C6_0 88
#define CLK_I3C7_0 89
#define CLK_GEM0_0 0U
#define CLK_GEM0_1 1U
#define CLK_GEM0_2 2U
#define CLK_GEM0_3 3U
#define CLK_GEM0_4 4U
#define CLK_GEM1_0 5U
#define CLK_GEM1_1 6U
#define CLK_GEM1_2 7U
#define CLK_GEM1_3 8U
#define CLK_GEM1_4 9U
#define CLK_SERIAL0_0 10U
#define CLK_SERIAL0_1 11U
#define CLK_SERIAL1_0 12U
#define CLK_SERIAL1_1 13U
#define CLK_UFS0_0 14U
#define CLK_UFS0_1 15U
#define CLK_UFS0_2 16U
#define CLK_USB0_0 17U
#define CLK_USB0_1 18U
#define CLK_USB0_2 19U
#define CLK_USB1_0 20U
#define CLK_USB1_1 21U
#define CLK_USB1_2 22U
#define CLK_MMC0_0 23U
#define CLK_MMC0_1 24U
#define CLK_MMC0_2 25U
#define CLK_MMC1_0 26U
#define CLK_MMC1_1 27U
#define CLK_MMC1_2 28U
#define CLK_TTC0_0 29U
#define CLK_TTC1_0 30U
#define CLK_TTC2_0 31U
#define CLK_TTC3_0 32U
#define CLK_TTC4_0 33U
#define CLK_TTC5_0 34U
#define CLK_TTC6_0 35U
#define CLK_TTC7_0 36U
#define CLK_I2C0_0 37U
#define CLK_I2C1_0 38U
#define CLK_I2C2_0 39U
#define CLK_I2C3_0 40U
#define CLK_I2C4_0 41U
#define CLK_I2C5_0 42U
#define CLK_I2C6_0 43U
#define CLK_I2C7_0 44U
#define CLK_OSPI0_0 45U
#define CLK_QSPI0_0 46U
#define CLK_QSPI0_1 47U
#define CLK_WWDT0_0 48U
#define CLK_WWDT1_0 49U
#define CLK_WWDT2_0 50U
#define CLK_WWDT3_0 51U
#define CLK_ADMA0_0 52U
#define CLK_ADMA0_1 53U
#define CLK_ADMA1_0 54U
#define CLK_ADMA1_1 55U
#define CLK_ADMA2_0 56U
#define CLK_ADMA2_1 57U
#define CLK_ADMA3_0 58U
#define CLK_ADMA3_1 59U
#define CLK_ADMA4_0 60U
#define CLK_ADMA4_1 61U
#define CLK_ADMA5_0 62U
#define CLK_ADMA5_1 63U
#define CLK_ADMA6_0 64U
#define CLK_ADMA6_1 65U
#define CLK_ADMA7_0 66U
#define CLK_ADMA7_1 67U
#define CLK_CAN0_0 68U
#define CLK_CAN0_1 69U
#define CLK_CAN1_0 70U
#define CLK_CAN1_1 71U
#define CLK_CAN2_0 72U
#define CLK_CAN2_1 73U
#define CLK_CAN3_0 74U
#define CLK_CAN3_1 75U
#define CLK_PS_GPIO_0 76U
#define CLK_PMC_GPIO_0 77U
#define CLK_SPI0_0 78U
#define CLK_SPI0_1 79U
#define CLK_SPI1_0 80U
#define CLK_SPI1_1 81U
#define CLK_I3C0_0 82U
#define CLK_I3C1_0 83U
#define CLK_I3C2_0 84U
#define CLK_I3C3_0 85U
#define CLK_I3C4_0 86U
#define CLK_I3C5_0 87U
#define CLK_I3C6_0 88U
#define CLK_I3C7_0 89U
#define RESET_GEM0_0 0
#define RESET_GEM1_0 1

12
plat/amd/versal2/plat_psci.c
View file

@ -35,9 +35,9 @@ static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr)
{
uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr) & ~BIT(MPIDR_MT_BIT);
uint32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER;
uint32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER;
int32_t cpu_id = plat_core_pos_by_mpidr(mpidr) & ~BIT(MPIDR_MT_BIT);
int32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER;
int32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER;
uintptr_t apu_cluster_base = 0, apu_pcli_base, apu_pcli_cluster = 0;
uintptr_t rst_apu_cluster = PSX_CRF + RST_APU0_OFFSET + ((uint64_t)cluster * 0x4U);
@ -48,7 +48,7 @@ static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr)
return PSCI_E_INTERN_FAIL;
}
if (cluster > 3) {
if (cluster > 3U) {
panic();
}
@ -178,9 +178,9 @@ static int32_t no_pm_ioctl(uint32_t device_id, uint32_t ioctl_id,
ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_TX_RX_CONFIG_RDY);
break;
case IOCTL_UFS_SRAM_CSR_SEL:
if (arg1 == 1) {
if (arg1 == 1U) {
ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_SRAM_CSR);
} else if (arg1 == 0) {
} else if (arg1 == 0U) {
mmio_write_32(PMXC_IOU_SLCR_SRAM_CSR, arg2);
}
break;

2
plat/amd/versal2/scmi.c
View file

@ -293,7 +293,7 @@ int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
return SCMI_NOT_FOUND;
}
if (start_idx > 0) {
if (start_idx > 0U) {
return SCMI_OUT_OF_RANGE;
}

2
plat/amd/versal2/sip_svc_setup.c
View file

@ -71,7 +71,7 @@ static uintptr_t sip_svc_smc_handler(uint32_t smc_fid,
VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
smc_fid, x1, x2, x3, x4);
if ((smc_fid & SIP_FID_MASK) != 0) {
if ((smc_fid & SIP_FID_MASK) != 0U) {
WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}