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https://github.com/ARM-software/arm-trusted-firmware.git
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fbc415d204
This corrects the MISRA violation C2012-10.4: Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: Ia352e3cf261b52777c1c431701e1e6c3be9cd279 Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
152 lines
3.5 KiB
C
152 lines
3.5 KiB
C
/*
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* Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <def.h>
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#include <plat_common.h>
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#include <plat_ipi.h>
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#include <plat_private.h>
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uint32_t platform_id, platform_version;
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/*
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* Table of regions to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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* configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t plat_mmap[] = {
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MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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#if TRANSFER_LIST
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MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_BASE + FW_HANDOFF_SIZE,
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MT_MEMORY | MT_RW | MT_NS),
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#endif
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{ 0 }
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};
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const mmap_region_t *plat_get_mmap(void)
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{
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return plat_mmap;
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}
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/* For saving cpu clock for certain platform */
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uint32_t cpu_clock;
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const char *board_name_decode(void)
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{
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const char *platform;
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switch (platform_id) {
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case SPP:
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platform = "IPP";
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break;
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case EMU:
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platform = "EMU";
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break;
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case SILICON:
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platform = "Silicon";
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break;
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case QEMU:
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platform = "QEMU";
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break;
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default:
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platform = "Unknown";
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}
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return platform;
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}
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void board_detection(void)
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{
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uint32_t version_type;
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version_type = mmio_read_32(PMC_TAP_VERSION);
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platform_id = FIELD_GET((uint32_t)PLATFORM_MASK, version_type);
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platform_version = FIELD_GET((uint32_t)PLATFORM_VERSION_MASK, version_type);
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if (platform_id == QEMU_COSIM) {
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platform_id = QEMU;
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}
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/* Make sure that console is setup to see this message */
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VERBOSE("Platform id: %d version: %d.%d\n", platform_id,
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platform_version / 10U, platform_version % 10U);
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}
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uint32_t get_uart_clk(void)
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{
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uint32_t uart_clock = 0;
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switch (platform_id) {
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case SPP:
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case SPP_MMD:
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uart_clock = cpu_clock;
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break;
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case EMU:
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case EMU_MMD:
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uart_clock = 25000000;
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break;
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case QEMU:
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/* Random values now */
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uart_clock = 25000000;
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break;
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case SILICON:
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uart_clock = 100000000;
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break;
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default:
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panic();
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}
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return uart_clock;
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}
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void config_setup(void)
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{
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uint32_t val;
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uintptr_t crl_base, iou_scntrs_base, psx_base;
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crl_base = CRL;
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iou_scntrs_base = IOU_SCNTRS;
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psx_base = PSX_CRF;
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/* Reset for system timestamp generator in FPX */
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mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0);
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/* Global timer init - Program time stamp reference clk */
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val = mmio_read_32(crl_base + CRL_TIMESTAMP_REF_CTRL_OFFSET);
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val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
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mmio_write_32(crl_base + CRL_TIMESTAMP_REF_CTRL_OFFSET, val);
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/* Clear reset of timestamp reg */
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mmio_write_32(crl_base + CRL_RST_TIMESTAMP_OFFSET, 0);
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/* Program freq register in System counter and enable system counter. */
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mmio_write_32(iou_scntrs_base + IOU_SCNTRS_BASE_FREQ_OFFSET,
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cpu_clock);
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mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
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IOU_SCNTRS_CONTROL_EN);
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generic_delay_timer_init();
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/* Configure IPI data */
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soc_ipi_config_table_init();
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}
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uint32_t plat_get_syscnt_freq2(void)
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{
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return cpu_clock;
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}
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