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feat(mt8196): enable apusys mailbox mpu protection

Browse source 
Enable mt8196 apusys mailbox mpu protection and
move the mt8188 setting to platform folder

Change-Id: I76b68318bb88e56b12cdacd9e2b998699ca6b48e
Signed-off-by: Karl Li <karl.li@mediatek.com>
This commit is contained in:
Karl Li 2024-11-14 16:18:54 +08:00
parent 9059a375ee
commit 83f836c962
8 changed files with 178 additions and 20 deletions
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3
plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
* Copyright (c) 2023-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -14,6 +14,7 @@
#include "apusys.h"
#include "apusys_rv.h"
#include "apusys_rv_mbox_mpu.h"
#include "apusys_rv_pwr_ctrl.h"
#include "emi_mpu.h"
static spinlock_t apusys_rv_lock;

19
plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
* Copyright (c) 2023-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -88,23 +88,6 @@
#define WDT_INT_W1C (1)
#define WDT_EN BIT(31)
/* APU MBOX */
#define MBOX_FUNC_CFG (0xb0)
#define MBOX_DOMAIN_CFG (0xe0)
#define MBOX_CTRL_LOCK BIT(0)
#define MBOX_NO_MPU_SHIFT (16)
#define MBOX_RX_NS_SHIFT (16)
#define MBOX_RX_DOMAIN_SHIFT (17)
#define MBOX_TX_NS_SHIFT (24)
#define MBOX_TX_DOMAIN_SHIFT (25)
#define MBOX_SIZE (0x100)
#define MBOX_NUM (8)
#define APU_MBOX(i) (((i) < MBOX_NUM) ? (APU_MBOX0 + MBOX_SIZE * (i)) : \
(APU_MBOX1 + MBOX_SIZE * ((i) - MBOX_NUM)))
#define APU_MBOX_FUNC_CFG(i) (APU_MBOX(i) + MBOX_FUNC_CFG)
#define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG)
void apusys_rv_mbox_mpu_init(void);
int apusys_kernel_apusys_rv_setup_reviser(void);
int apusys_kernel_apusys_rv_reset_mp(void);

2
plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv_mbox_mpu.h → plat/mediatek/drivers/apusys/mt8188/apusys_rv_mbox_mpu.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
* Copyright (c) 2023-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

31
plat/mediatek/drivers/apusys/mt8188/apusys_rv_pwr_ctrl.h Normal file
View file

@ -0,0 +1,31 @@
/*
* Copyright (c) 2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef APUSYS_RV_PWR_CTL_H
#define APUSYS_RV_PWR_CTL_H
/* APU MBOX */
#define MBOX_FUNC_CFG (0xb0)
#define MBOX_DOMAIN_CFG (0xe0)
#define MBOX_CTRL_LOCK BIT(0)
#define MBOX_NO_MPU_SHIFT (16)
#define MBOX_RX_NS_SHIFT (16)
#define MBOX_RX_DOMAIN_SHIFT (17)
#define MBOX_TX_NS_SHIFT (24)
#define MBOX_TX_DOMAIN_SHIFT (25)
#define MBOX_SIZE (0x100)
#define MBOX_NUM (8)
#define APU_MBOX(i) (((i) < MBOX_NUM) ? (APU_MBOX0 + MBOX_SIZE * (i)) : \
(APU_MBOX1 + MBOX_SIZE * ((i) - MBOX_NUM)))
#define APU_MBOX_FUNC_CFG(i) (APU_MBOX(i) + MBOX_FUNC_CFG)
#define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG)
#define HW_SEM_TIMEOUT (0)
int apusys_rv_pwr_ctrl(uint32_t op);
#endif /* APUSYS_RV_PWR_CTL_H */

55
plat/mediatek/drivers/apusys/mt8196/apusys_rv_mbox_mpu.h Normal file
View file

@ -0,0 +1,55 @@
/*
* Copyright (c) 2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef APUSYS_RV_MBOX_MPU_H
#define APUSYS_RV_MBOX_MPU_H
#define MPU_EN (0)
#define MPU_DIS (1)
#define MBOX0_TX_DOMAIN (0)
#define MBOX0_TX_NS (1)
#define MBOX1_TX_DOMAIN (11)
#define MBOX1_TX_NS (1)
#define MBOX3_TX_DOMAIN (3)
#define MBOX3_TX_NS (0)
#define MBOX4_RX_DOMAIN (0)
#define MBOX4_RX_NS (0)
#define MBOX5_TX_DOMAIN (8)
#define MBOX5_TX_NS (0)
#define MBOX6_TX_DOMAIN (4)
#define MBOX6_TX_NS (1)
#define MBOX7_RX_DOMAIN (0)
#define MBOX7_RX_NS (0)
#define MBOXN_RX_DOMAIN (5)
#define MBOXN_RX_NS (0)
#define MBOXN_TX_DOMAIN (0)
#define MBOXN_TX_NS (0)
struct mbox_mpu_setting {
uint32_t no_mpu;
uint32_t rx_ns;
uint32_t rx_domain;
uint32_t tx_ns;
uint32_t tx_domain;
};
static const struct mbox_mpu_setting mbox_mpu_setting_tab[] = {
/* no_mpu, rx_ns, rx_domain, tx_ns, tx_domain */
{MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX0_TX_NS, MBOX0_TX_DOMAIN},
{MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX1_TX_NS, MBOX1_TX_DOMAIN},
{MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN},
{MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX3_TX_NS, MBOX3_TX_DOMAIN},
{MPU_DIS, MBOX4_RX_NS, MBOX4_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN},
{MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX5_TX_NS, MBOX5_TX_DOMAIN},
{MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX6_TX_NS, MBOX6_TX_DOMAIN},
{MPU_DIS, MBOX7_RX_NS, MBOX7_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN},
{MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN},
{MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN},
};
#define APU_MBOX_NUM ARRAY_SIZE(mbox_mpu_setting_tab)
#endif /* APUSYS_RV_MBOX_MPU_H */

81
plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h Normal file
View file

@ -0,0 +1,81 @@
/*
* Copyright (c) 2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef APUSYS_RV_PWR_CTL_H
#define APUSYS_RV_PWR_CTL_H
#include <platform_def.h>
#define SUPPORT_APU_CLEAR_MBOX_DUMMY (1)
enum apu_hw_sem_sys_id {
APU_HW_SEM_SYS_APU = 0UL, /* mbox0 */
APU_HW_SEM_SYS_GZ = 1UL, /* mbox1 */
APU_HW_SEM_SYS_SCP = 3UL, /* mbox3 */
APU_HW_SEM_SYS_APMCU = 11UL, /* mbox11 */
};
int apusys_rv_pwr_ctrl(uint32_t op);
int rv_iommu_hw_sem_unlock(void);
int rv_iommu_hw_sem_trylock(void);
int apu_hw_sema_ctl(uint32_t sem_addr, uint8_t usr_bit, uint8_t ctl, uint32_t timeout,
uint8_t bypass);
#define HW_SEM_TIMEOUT (300) /* 300 us */
/* APU MBOX */
#define MBOX_WKUP_CFG (0x80)
#define MBOX_WKUP_MASK (0x84)
#define MBOX_FUNC_CFG (0xb0)
#define MBOX_DOMAIN_CFG (0xe0)
#define MBOX_CTRL_LOCK BIT(0)
#define MBOX_NO_MPU_SHIFT (16)
#define MBOX_RC_SHIFT (24)
#define MBOX_RX_NS_SHIFT (16)
#define MBOX_RX_DOMAIN_SHIFT (17)
#define MBOX_TX_NS_SHIFT (24)
#define MBOX_TX_DOMAIN_SHIFT (25)
#define APU_REG_AO_GLUE_CONFG (APU_AO_CTRL + 0x20)
#define ENABLE_INFRA_WA
enum apu_infra_bit_id {
APU_INFRA_SYS_APMCU = 1UL,
APU_INFRA_SYS_GZ = 2UL,
APU_INFRA_SYS_SCP = 3UL,
};
#define APU_MBOX(i) (APU_MBOX0 + 0x10000 * i)
#define APU_MBOX_FUNC_CFG(i) (APU_MBOX(i) + MBOX_FUNC_CFG)
#define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG)
#define APU_MBOX_WKUP_CFG(i) (APU_MBOX(i) + MBOX_WKUP_CFG)
/* bypass mbox register Dump for secure master */
#define APU_MBOX_DBG_EN (0x190f2380)
/* apu_mbox register definition for mbox addr change*/
#define APU_MBOX_SEMA0_CTRL (0x090)
#define APU_MBOX_SEMA0_RST (0x094)
#define APU_MBOX_SEMA0_STA (0x098)
#define APU_MBOX_SEMA1_CTRL (0x0A0)
#define APU_MBOX_SEMA1_RST (0x0A4)
#define APU_MBOX_SEMA1_STA (0x0A8)
#define APU_MBOX_DUMMY (0x040)
#define APU_MBOX_OFFSET(i) (0x10000 * i)
/* apu infra workaround */
#define APU_INFRA_DISABLE (APU_INFRA_BASE + 0xC18)
#define APU_INFRA_ENABLE (APU_INFRA_BASE + 0xC14)
#define APU_INFRA_STATUS (APU_INFRA_BASE + 0xC10)
#define APU_INFRA_HW_SEM (APUSYS_CE_BASE + 0xE00)
#define APU_RPC_STATUS (0x190f0044)
#endif /* APUSYS_RV_PWR_CTL_H */

5
plat/mediatek/mt8196/include/platform_def.h
View file

@ -35,11 +35,16 @@
******************************************************************************/
#define APUSYS_BASE (IO_PHYS + 0x09000000)
#define APUSYS_CE_BASE (IO_PHYS + 0x090B0000)
#define APU_AO_CTRL (IO_PHYS + 0x090F2000)
#define APU_SEC_CON (IO_PHYS + 0x090F5000)
#define APUSYS_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090FC000)
#define APU_MBOX0 (0x4C200000)
#define APU_MBOX0_SZ (0x100000)
#define APU_INFRA_BASE (0x1002C000)
#define APU_INFRA_SZ (0x1000)
/*******************************************************************************
* SPM related constants
******************************************************************************/

2
plat/mediatek/mt8196/plat_mmap.c
View file

@ -21,6 +21,8 @@ static const mmap_region_t plat_mmap[] = {
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(EDP_SEC_BASE, EDP_SEC_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(APU_MBOX0, APU_MBOX0_SZ,
MT_DEVICE | MT_RW | MT_SECURE),
{ 0 }
};
DECLARE_MTK_MMAP_REGIONS(plat_mmap);