u-boot was crashing in qemu as the modeled hardware enforced overly
strict memory reads.
While this code will work on existing hardware, fix to avoid future issues.
Fixes: 12770d0df0 ("ast2600: spl: Add boot mode detection")
Link: https://gitlab.com/qemu-project/qemu/-/issues/2636
Signed-off-by: Joel Stanley <joel@jms.id.au>
Janne Grunau <j@jannau.net> says:
Starting with v2024.10 dev_iommu_dma_unmap calls during device removal
trigger a NULL pointer dereference in the Apple dart iommu driver. The
iommu device is removed before its user. The sparsely used DM_FLAG_VITAL
flag is intended to describe this dependency. Add it to the driver.
Adding this flag is unfortunately not enough since the boot routines
except the arm one simply remove all drivers. Add and use a new function
which calls
dm_remove_devioce_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL);
dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
to ensure this order dependency is head consistently.
Link: https://lore.kernel.org/r/20241123-iommu_apple_dart_ordering-v2-0-cc2ade6dde97@jannau.net
This replaces dm_remove_devices_flags() calls in all boot
implementations to ensure non vital devices are consistently removed
first. All boot implementation except arch/arm/lib/bootm.c currently
just call dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL). This can result
in crashes when dependencies between devices exists. The driver model's
design document describes DM_FLAG_VITAL as "indicates that the device is
'vital' to the operation of other devices". Device removal at boot
should follow this.
Instead of adding dm_remove_devices_flags() with (DM_REMOVE_ACTIVE_ALL |
DM_REMOVE_NON_VITAL) everywhere add dm_remove_devices_active() which
does this.
Fixes a NULL pointer deref in the apple dart IOMMU driver during EFI
boot. The xhci-pci (driver which depends on the IOMMU to work) removes
its mapping on removal. This explodes when the IOMMU device was removed
first.
dm_remove_devices_flags() is kept since it is used for testing of
device_remove() calls in dm.
Signed-off-by: Janne Grunau <j@jannau.net>
Since 50cdd3f74a ("clk: imx: clk-imx8mn Fix nand and spi clock parent"),
drivers/clk/imx/clk-imx8mn.c clk_get_by_name(dev, "osc_24m", &osc_24m_clk)
fails with error -22 EINVAL in SPL. This is because clk_get_by_name() in the
end calls fdtdec_parse_phandle_with_args(), which iterates over all phandles
in clock-controller@30380000 { clocks = <&osc_32k>, <&osc_24m>, ... } node
'clocks' property in an attempt to find the "osc_24m" clock, but fails to
resolve the &osc_32k phandle and returns with -EINVAL.
Include the osc_32k clock in SPL DTs as a low risk fix for v2025.01 release.
This way, fdtdec_parse_phandle_with_args() can resolve both the osc_32k and
following osc_24m phandle and successfully look up the osc_24m clock.
Fixes: 50cdd3f74a ("clk: imx: clk-imx8mn Fix nand and spi clock parent")
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mn-beacon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/23474
- UFS support is enabled for SC7280 and SM8150 platforms.
- Qualcomm dt-bindings headers are all dropped in favour of
dts/upstream.
- The SMMU driver now correctly handles stream ID 0 and is disabled in
EL2.
- Initial support for capsule updates (using the new dynamic UUIDs) is
added for the RB3 Gen 2 board alongside a new SCSI backend for DFU.
- CONFIG_PINCONF is enabled in qcom_defconfig.
- The vqmmc supply is now enabled for sdcard support on boards that need
it.
- A quirk is added for reading GPIOs on the PM8550 PMIC
Qualcomm boards flash U-Boot a variety of partitions, implement support
for determining which slot U-Boot is running from, finding the correct
partition for that slot and configuring the appropriate DFU string.
Initially, we only support the RB3 Gen 2 where U-Boot is flashed to the
UEFI partition, and ignore handling of slots. In the future we will
additionally support booting U-Boot from other partitions (e.g. boot)
and correct handling for A/B.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Set LOG_CATEGORY and pr_fmt. Also fix the time.h include.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Fastboot is very hungry when it flashes larges chunks, and 8MiB
is way too small, allocate a much bigger size like other platforms
using Fastboot.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # rb1
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Fix the critical thermal threshold for i.MX processors, this was changed
while moving the code from imx8m/imx9 directories into a shared place.
There is no need to keep the critical threshold 5 degrees less than the
SoC maximum temperature threshold, what is actually going to happen in
practice is that we are going to power-off the board when the SoC is
still within its working temperature range.
In addition to that this is a change in the actual behavior, that is
introducing a regression to users, and it was hidden within a software
refactoring.
Fixes: d0fe80890a ("imx: Generalize fixup_thermal_trips")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Add native support of the bootcount mechanism in the ZynqMP by
utilising internal PMU registers. The Persistent Global Storage
Registers of the Platform Management Unit can keep their value
during reboot cycles unless there is a POR reset, making them
appropriate for the bootcount mechanism.
Signed-off-by: Vasileios Amoiridis <vasileios.amoiridis@cern.ch>
Reviewed-by: Heiko Schocher <hs@denx.de>
Link: https://lore.kernel.org/r/20241105132744.1572759-2-vassilisamir@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The cpu release command for r5 mode (lockstep/split) argument
accepts only string. But the zynqmp tcminit command accepts
string or number for r5 mode (lockstep/split or 0/1) argument.
To fix the r5 mode argument, the common argument (lockstep/split
or 0/1) is used across different u-boot commands. Use the strcmp()
instead of strncmp() to make uniform the r5 mode (lockstep/split
or 0/1) for the zynqmp tcminit and cpu release command.
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20241104122750.96251-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Wadim Egorov <w.egorov@phytec.de> says:
Our SoMs are available in multiple configurations, managed via device
tree overlays. To determine the specific variant in use, we read the
EEPROM and apply the appropriate overlays during boot to the device tree
used by the OS.
Apply overlays for phyCORE-AM62x and phyCORE-AM64x SoMs.
Future K3 SoMs will be able to reuse this logic and overlays.
Link: https://lore.kernel.org/r/20241030164815.1763506-1-w.egorov@phytec.de
Include SoM dt-overlays that handle variants of our SoMs into
u-boot's FIT image.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Include SoM dt-overlays that handle variants of our SoMs into
u-boot's FIT image.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Sort the DTSI alphabetically. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The ethernet0_rmii_pins_a pinmux change has no effect on any
DHSOM based hardware. The mco2_pins_a and mco2_sleep_pins_a
are both part of stm32mp15-pinctrl.dtsi . Drop both pinmux
changes.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Remove unused local DT copies after the OF_UPSTREAM conversion.
Fixes: cccb29fc12 ("ARM: dts: stm32: Switch to using upstream DT on DH STM32 DHSOM")
Reported-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
In previous version of pwm driver, the polarity of pwm were implemented
in reverse. In recent release, that issue in the driver is fixed,
therefore, correctly set the polarity in the device tree.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3e8e38b77101335f86bca0f05b3988877bb12993.1729766551.git.michal.simek@amd.com
Use RTC available in HW on Kria SOM without using emulation that's why
configure it properly and disable emulated one.
Power on reset value of RTC Calibration register without battery backup is
not matching with crystal frequency which leads to RTC time drift. That's
why write CALIB_WRITE register with crystal frequency (0x7FFF). There is
also an option to write zero so that Linux will set default value (0x7FFF)
in driver probe but calibration 0 is not permited by DT schema.
Co-developed-by: Srinivas Goud <srinivas.goud@amd.com>
Signed-off-by: Srinivas Goud <srinivas.goud@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9b684faeec85381b9b8fe796aaebc2ee79f17b8e.1729663761.git.michal.simek@amd.com
If TPL_GPIO and TPL_PINCTRL_ROCKCHIP are enabled and a sysreset-gpio is
provided in the TPL Device Tree, this will trigger a system reset
similar to what's currently been done in SPL whenever the RK3399 "warm"
boots. Because there's currently only one user of sysreset-gpio logic,
and TPL is enabled on that board, so let's migrate the logic and that
board to do it in TPL.
There are three reasons for moving this earlier:
- faster boot time as we don't need to reach SPL to be able to reset the
system on a condition we know is already met in TPL,
- have less code to be impacted by the issue this system reset works
around (that is, "unclean" SoC registers after a reboot),
- less confusion around the reason for restarting. Indeed when done from
SPL, the following log can be observed:
"""
U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45)
Channel 0: DDR3, 666MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Channel 1: DDR3, 666MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
256B stride
Trying to boot from BOOTROM
Returning to boot ROM...
U-Boot SPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45 +0100)
Trying to boot from MMC2
U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45)
"""
possibly hinting at an issue within the SPL when loading the fitImage
from MMC2 instead of the normal course of events (a system reset).
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Paul Kocialkowski <paulk@sys-base.io>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This defines a weak tpl_board_init function that can be used for running
board/SoC-specific code before the DRAM init happens, similarly to
spl_board_init() for SPL.
Reviewed-by: Paul Kocialkowski <paulk@sys-base.io>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
To prepare to support forcing power on reset from TPL which would have
the exact same logic, just in an earlier stage, let's merge the CRU
check that triggers the power on reset with the rest of the logic.
Reviewed-by: Paul Kocialkowski <paulk@sys-base.io>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The FriendlyElec NanoPi R2S Plus is a single-board computer based on
Rockchip RK3328 SoC. It features e.g. 1 GB DDR4 RAM, 32 GB eMMC,
SD-card, 2x GbE LAN, optional M.2 SDIO Wi-Fi and 2x USB 2.0 host.
Features tested on a NanoPi R2S Plus 2309:
- SD-card boot
- eMMC boot
- Ethernet
- USB gadget
- USB host
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for Cool Pi GenBook, it works as a carrier board
connect with CM5 SOM.
Specification:
- Rockchip RK3588
- LPDDR5X 8/32 GB
- eMMC 64 GB
- HDMI Type A out x 1
- USB 3.0 Host x 1
- USB-C 3.0 with DisplayPort AltMode
- PCIE M.2 E Key for RTL8852BE Wireless connection
- PCIE M.2 M Key for NVME connection
- eDP panel with 1920x1080
Tested by Armbian boot on USB disk.
Change-Id: I4d9b8572dc7c400077dde666633f3fea1b47dd03
Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The Qnap TS433 is a 4-bay NAS based around the RK3568.
Two SATA bays are connected to the RK3568's own SATA controllers while
the other two are connected to a JMicron SATA controller living on the
PCIe bus.
It provides one 2.5Gb and one 1Gb ethernet port as well as 3 usb ports.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
For upstream Linux kernel we use below DTBs for HiHope boards:
- r8a774a1-hihope-rzg2m-ex.dtb
- r8a774e1-hihope-rzg2h-ex.dtb
- r8a774b1-hihope-rzg2n-ex.dtb
Update the CONFIG_OF_LIST to match the above. Now that we have switched
upstream DTS, drop deleting the nodes and also rename the
r8a774*-u-boot.dtsi files to r8a774*-ex-u-boot.dtsi to match the OF_LIST
files so that the `bootph-all` property gets applied to required nodes
in upstream DTS.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
When support for the Renesas RZ/G2L SoC was added, the GICR base address
for CPU1 was accidentally used. We should instead supply the GICR base
address for CPU0 so that interrupts are correctly configured for the
CPU core that U-Boot is actually using.
Fixes: 387d4275ab ("arm: rmobile: Add basic RZ/G2L family support")
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
We are now using the dts/upstream subtree for the RZ/G2L SoC family so
we can drop unused devicetree files from arch/arm/dts.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Working with HAB on the i.MX8MP we've encountered a case where a board
that successfully authenticates u-boot when booting Linux subsequently
fails to properly bring up the RTC.
The RTC registers live in the low-power block of the Secure Non-Volatile
Storage (SNVS) block.
The root cause of the error has been traced to the HAB handing off the
SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the
Non-Privileged Software Access Enable bit is zero.
Configure SNVS to allow unpriv access to SNVS LP for imx8m and imx8mp.
This commit generalizes 723f8359c1 ("imx: mx7: snvs: Add an SNVS init
routine") to also be used on i.MX8M SoCs, and was testeed on i.MX8MP.
Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
Commit 723f8359c1 ("imx: mx7: snvs: Add an SNVS init routine") noted
that the init_snvs() call likely applies to other i.MX processors, and
this has been found to be true for i.MX8MP.
Move snvs module for future re-use.
Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
Enable OF_UPSTREAM to use upstream DT and add nxp/imx/ prefix to the
DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/
including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory.
Signed-off-by: Marek Vasut <marex@denx.de>
Improve "mmcautodetect=yes" boot mode autodetection to able to use it
if CONFIG_ENV_IS_NOWHERE=y is used for i.MX9 SoCs and i.MX93 EVK board.
If both CONFIG_ENV_IS_IN_MMC=y and CONFIG_ENV_IS_NOWHERE=y are in the
defconfig, CONFIG_ENV_IS_IN_MMC=y will be overiden default
CONFIG_ENV_IS_NOWHERE settings.
Goal is in this patch to able to use the boot mode autodetection
if defconfig use only CONFIG_ENV_IS_NOWHERE=y option
(without CONFIG_ENV_IS_IN_MMC) for any i.MX9 SoC.
Signed-off-by: Benjamin Szőke <egyszeregy@freemail.hu>
The decision on whether HAB is enabled is solely based on the SEC_CONFIG
fuse. The HAB FIELD_RETURN feature is able to permanently disable HAB on
a CPU, after which it is able to boot unsigned firmware. U-Boot however
does not take into account the FIELD_RETURN mode, and refuses to boot
unsigned software when the feature is enabled.
Also take the FIELD_RETURN fuse into account when deciding whether HAB
is enabled. When The FIELD_RETURN fuse is blown, HAB is not enabled.
Tested on i.MX8M Mini, i.MX8M Plus, i.MX8M Nano and i.MX6ULL
Signed-off-by: Paul Geurts <paul.geurts@prodrive-technologies.com>
The imx_sec_config_fuse_t structure is not specific to the sec_config
fuse, but can be used for all fuse words.
Rename the structure to a more generic name to be reused for other
fuses.
Signed-off-by: Paul Geurts <paul.geurts@prodrive-technologies.com>
Leo Yan <leo.yan@arm.com> says:
This patch series is to refine the booting on Arm Total Compuate
platform.
It changes to use the info passed in DTB for initialization DRAM info,
and dynamically initializes the booting envoironment variables.
Another big change is to use an envoironment file for boot commands,
based on it, the series extends to support multiple block devices
(MMC and virtio). And the env file is extended for booting Debian.
The last commit is to update memory mapping info based on the DRAM info
passed via DT binding.
Link: https://lore.kernel.org/r/20241025171821.624702-1-leo.yan@arm.com
Initialize the environment variables 'fdt_addr_r' and 'kernel_addr_r'
during the misc init phase. The static configurations are not needed,
remove them.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
On Total Compute, TF-A passes the info via DT binding for the hardware
description - includes the serial, memory, and arm_ffa nodes.
This commit initializes the fdt base address based on the passed the
register x1.
The similar implementation has already been done for the raspberry pi,
so borrow a lot of it.
Co-developed-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Create an SoC R5 dtsi file that could be used at board level R5 files. This
would help in keeping the SoC level changes in sync across board files.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Bastien Curutchet <bastien.curutchet@bootlin.com> says:
Hi all,
This patch series aims to add DM support for the AEMIF controller that
can be found in the DaVinci SoCs.
This controller has already a driver used by the Keystone SoCs so I
add my work to it.
As we can now easily import Linux device-trees, I try to stick the
most I can to the Linux bindings of the AEMIF controller. To do so I add
an 'intermediate' driver called 'ti-aemif-cs'. It's in charge of
configuring timings for a given chip select of the AEMIF controller.
Link: https://lore.kernel.org/r/20241021151330.1860929-1-bastien.curutchet@bootlin.com
AEMIF controller is present on other SoCs than the Keystone ones.
Remove Keystone specificities from the driver to be able to use it from
other architectures.
Adapt the ks2_evm/board.c to fit the new driver.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently, a number of generic cache related functions have their common
prototype declared in include/cpu_func.h. Move the current set of
noncached functions there as well to match.
Signed-off-by: Tom Rini <trini@konsulko.com>
The Emcraft Systems NavQ+ kit is a mobile robotics platform
based on NXP i.MX8 MPlus SoC.
The following interfaces and devices are enabled:
- eMMC
- Gigabit Ethernet (through eQOS interface)
- SD-Card
- UART console
The device tree file is taken from upstream Linux Kernel
through OF_UPSTREAM
Signed-off-by: Gilles Talis <gilles.talis@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Jan Kiszka <jan.kiszka@siemens.com> says:
This adds support for the new IOT2050 SM variant, introduces a sysinfo
driver which also permits SMBIOS support and switches the board to
OF_UPSTREAM. There are some further fixes for the boards included as well.
Not yet included is configuration support for DMA isolation via the PVU as
this depends on not yet merged DT bindings and another overlay.
[trini: This is just the first 10 patches in the series for now]
Link: https://lore.kernel.org/r/cover.1729577070.git.jan.kiszka@siemens.com
