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Merge patch series "Apply SoM overlays on phyCORE-AM6xx SoMs"
Wadim Egorov <w.egorov@phytec.de> says: Our SoMs are available in multiple configurations, managed via device tree overlays. To determine the specific variant in use, we read the EEPROM and apply the appropriate overlays during boot to the device tree used by the OS. Apply overlays for phyCORE-AM62x and phyCORE-AM64x SoMs. Future K3 SoMs will be able to reuse this logic and overlays. Link: https://lore.kernel.org/r/20241030164815.1763506-1-w.egorov@phytec.de
This commit is contained in:
Tom Rini
commit
a45d823c02
5 changed files with 182 additions and 2 deletions
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@ -301,6 +301,54 @@
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description = "U-Boot for phyCORE-AM62x";
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};
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som-no-rtc {
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description = "k3-am6xx-phycore-disable-rtc";
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type = "flat_dt";
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compression = "none";
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load = <0x8F000000>;
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arch = "arm";
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blob-ext {
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filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
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};
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};
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som-no-spi {
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description = "k3-am6xx-phycore-disable-spi-nor";
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type = "flat_dt";
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compression = "none";
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load = <0x8F001000>;
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arch = "arm";
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blob-ext {
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filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
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};
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};
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som-no-eth {
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description = "k3-am6xx-phycore-disable-eth-phy";
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type = "flat_dt";
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compression = "none";
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load = <0x8F002000>;
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arch = "arm";
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blob-ext {
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filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
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};
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};
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som-qspi {
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description = "k3-am6xx-phycore-qspi-nor";
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type = "flat_dt";
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compression = "none";
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load = <0x8F003000>;
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arch = "arm";
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blob-ext {
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filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
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};
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};
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fdt-0 {
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description = "k3-am625-phyboard-lyra-rdk";
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type = "flat_dt";
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@ -325,7 +373,11 @@
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conf-0 {
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description = "k3-am625-phyboard-lyra-rdk";
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firmware = "uboot";
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loadables = "uboot";
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loadables = "uboot",
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"som-no-rtc",
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"som-no-spi",
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"som-no-eth",
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"som-qspi";
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fdt = "fdt-0";
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};
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};
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@ -344,6 +344,54 @@
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description = "U-Boot for AM64 board";
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};
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som-no-rtc {
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description = "k3-am6xx-phycore-disable-rtc";
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type = "flat_dt";
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compression = "none";
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load = <0x8F000000>;
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arch = "arm";
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blob-ext {
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filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
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};
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};
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som-no-spi {
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description = "k3-am6xx-phycore-disable-spi-nor";
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type = "flat_dt";
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compression = "none";
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load = <0x8F001000>;
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arch = "arm";
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blob-ext {
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filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
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};
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};
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som-no-eth {
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description = "k3-am6xx-phycore-disable-eth-phy";
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type = "flat_dt";
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compression = "none";
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load = <0x8F002000>;
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arch = "arm";
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blob-ext {
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filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
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};
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};
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som-qspi {
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description = "k3-am6xx-phycore-qspi-nor";
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type = "flat_dt";
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compression = "none";
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load = <0x8F003000>;
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arch = "arm";
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blob-ext {
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filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
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};
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};
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fdt-0 {
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description = "k3-am642-phyboard-electra-rdk";
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type = "flat_dt";
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@ -368,7 +416,11 @@
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conf-0 {
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description = "k3-am642-phyboard-electra-rdk";
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firmware = "uboot";
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loadables = "uboot";
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loadables = "uboot",
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"som-no-rtc",
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"som-no-spi",
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"som-no-eth",
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"som-qspi";
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fdt = "fdt-0";
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};
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};
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@ -6,7 +6,9 @@
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#include <env_internal.h>
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#include <fdt_support.h>
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#include <dm/ofnode.h>
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#include <spl.h>
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#include <malloc.h>
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#include <asm/arch/hardware.h>
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#include "../am6_som_detection.h"
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@ -97,8 +99,79 @@ int board_late_init(void)
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#endif
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#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
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static int fdt_apply_overlay_from_fit(const char *overlay_path, void *fdt)
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{
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u64 loadaddr;
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ofnode node;
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int ret;
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node = ofnode_path(overlay_path);
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if (!ofnode_valid(node))
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return -FDT_ERR_NOTFOUND;
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ret = ofnode_read_u64(node, "load", &loadaddr);
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if (ret)
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return ret;
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return fdt_overlay_apply_verbose(fdt, (void *)loadaddr);
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}
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static void fdt_apply_som_overlays(void *blob)
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{
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void *fdt_copy;
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u32 fdt_size;
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struct phytec_eeprom_data data;
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int err;
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fdt_size = fdt_totalsize(blob);
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fdt_copy = malloc(fdt_size);
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if (!fdt_copy)
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goto fixup_error;
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memcpy(fdt_copy, blob, fdt_size);
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err = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR);
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if (err)
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goto fixup_error;
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if (phytec_get_am6_rtc(&data) == 0) {
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err = fdt_apply_overlay_from_fit("/fit-images/som-no-rtc", fdt_copy);
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if (err)
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goto fixup_error;
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}
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if (phytec_get_am6_spi(&data) == PHYTEC_EEPROM_VALUE_X) {
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err = fdt_apply_overlay_from_fit("/fit-images/som-no-spi", fdt_copy);
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if (err)
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goto fixup_error;
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}
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if (phytec_get_am6_eth(&data) == 0) {
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err = fdt_apply_overlay_from_fit("/fit-images/som-no-eth", fdt_copy);
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if (err)
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goto fixup_error;
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}
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if (phytec_am6_is_qspi(&data)) {
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err = fdt_apply_overlay_from_fit("/fit-images/som-qspi-nor", fdt_copy);
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if (err)
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goto fixup_error;
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}
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memcpy(blob, fdt_copy, fdt_size);
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cleanup:
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free(fdt_copy);
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return;
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fixup_error:
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pr_err("Failed to apply SoM overlays\n");
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goto cleanup;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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fdt_apply_som_overlays(blob);
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fdt_copy_fixed_partitions(blob);
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return 0;
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@ -72,6 +72,7 @@ CONFIG_CMD_SMC=y
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CONFIG_OF_CONTROL=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_MULTI_DTB_FIT=y
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CONFIG_OF_OVERLAY_LIST="ti/k3-am6xx-phycore-disable-spi-nor ti/k3-am6xx-phycore-disable-rtc ti/k3-am6xx-phycore-disable-eth-phy ti/k3-am6xx-phycore-qspi-nor"
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CONFIG_SPL_MULTI_DTB_FIT=y
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CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
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CONFIG_ENV_OVERWRITE=y
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@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=2
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CONFIG_SOC_K3_AM642=y
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CONFIG_K3_ATF_LOAD_ADDR=0x701c0000
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CONFIG_TARGET_PHYCORE_AM64X_A53=y
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CONFIG_PHYTEC_SOM_DETECTION=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
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CONFIG_ENV_SIZE=0x20000
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@ -77,6 +78,7 @@ CONFIG_CMD_TIME=y
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CONFIG_CMD_SMC=y
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CONFIG_OF_CONTROL=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_OVERLAY_LIST="ti/k3-am6xx-phycore-disable-spi-nor ti/k3-am6xx-phycore-disable-rtc ti/k3-am6xx-phycore-disable-eth-phy ti/k3-am6xx-phycore-qspi-nor"
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CONFIG_MULTI_DTB_FIT=y
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CONFIG_SPL_MULTI_DTB_FIT=y
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CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
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