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ARM: dts: Drop unused RZ/G2L devicetrees
We are now using the dts/upstream subtree for the RZ/G2L SoC family so we can drop unused devicetree files from arch/arm/dts. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Paul Barker
Marek Vasut
parent
7edcc241f3
commit
db3b17db5c
8 changed files with 0 additions and 2220 deletions
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@ -975,9 +975,6 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
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imxrt1020-evk.dtb \
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imxrt1170-evk.dtb \
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dtb-$(CONFIG_TARGET_RZG2L) += \
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r9a07g044l2-smarc.dts
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ifdef CONFIG_RCAR_64
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DTC_FLAGS += -R 4 -p 0x1000
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endif
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File diff suppressed because it is too large
Load diff
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@ -1,39 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G2L SMARC EVK board
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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/dts-v1/;
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/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
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#define PMOD1_SER0 1
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/*
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* To enable MTU3a PWM on PMOD0,
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* Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
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* enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
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*/
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#define PMOD_MTU3 0
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#if (PMOD_MTU3 && PMOD1_SER0)
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#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
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#endif
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#define MTU3_COUNTER_Z_PHASE_SIGNAL 0
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#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
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#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
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#endif
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#include "r9a07g044l2.dtsi"
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#include "rzg2l-smarc-som.dtsi"
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#include "rzg2l-smarc-pinfunction.dtsi"
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#include "rz-smarc-common.dtsi"
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#include "rzg2l-smarc.dtsi"
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/ {
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model = "Renesas SMARC EVK based on r9a07g044l2";
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compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
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};
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@ -1,13 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include "r9a07g044.dtsi"
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/ {
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compatible = "renesas,r9a07g044l2", "renesas,r9a07g044";
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};
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@ -1,183 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/{G2L,G2LC,V2L} SMARC EVK common parts
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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/*
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* SSI-WM8978
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*
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* This command is required when Playback/Capture
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*
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* amixer cset name='Left Input Mixer L2 Switch' on
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* amixer cset name='Right Input Mixer R2 Switch' on
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* amixer cset name='Headphone Playback Volume' 100
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* amixer cset name='PCM Volume' 100%
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* amixer cset name='Input PGA Volume' 25
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*
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*/
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/ {
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aliases {
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serial0 = &scif0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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snd_rzg2l: sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&cpu_dai>;
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simple-audio-card,frame-master = <&cpu_dai>;
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,widgets = "Microphone", "Microphone Jack";
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simple-audio-card,routing =
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"L2", "Mic Bias",
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"R2", "Mic Bias",
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"Mic Bias", "Microphone Jack";
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cpu_dai: simple-audio-card,cpu {
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};
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codec_dai: simple-audio-card,codec {
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clocks = <&versa3 2>;
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sound-dai = <&wm8978>;
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};
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};
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usb0_vbus_otg: regulator-usb0-vbus-otg {
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compatible = "regulator-fixed";
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regulator-name = "USB0_VBUS_OTG";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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vccq_sdhi1: regulator-vccq-sdhi1 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI1 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios-states = <1>;
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states = <3300000 1>, <1800000 0>;
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};
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x1: x1-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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&audio_clk1 {
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clock-frequency = <11289600>;
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};
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&audio_clk2 {
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clock-frequency = <12288000>;
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};
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&canfd {
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pinctrl-0 = <&can0_pins &can1_pins>;
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pinctrl-names = "default";
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status = "okay";
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channel0 {
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status = "okay";
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};
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channel1 {
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status = "okay";
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};
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};
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&ehci0 {
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dr_mode = "otg";
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status = "okay";
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};
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&ehci1 {
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status = "okay";
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};
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&hsusb {
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dr_mode = "otg";
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status = "okay";
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&ohci0 {
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dr_mode = "otg";
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status = "okay";
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};
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&ohci1 {
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status = "okay";
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};
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&phyrst {
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status = "okay";
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdhi1 {
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pinctrl-0 = <&sdhi1_pins>;
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pinctrl-1 = <&sdhi1_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <&vccq_sdhi1>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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&spi1 {
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pinctrl-0 = <&spi1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&usb2_phy0 {
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pinctrl-0 = <&usb0_pins>;
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pinctrl-names = "default";
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vbus-supply = <&usb0_vbus_otg>;
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status = "okay";
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};
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&usb2_phy1 {
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pinctrl-0 = <&usb1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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@ -1,157 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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&pinctrl {
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pinctrl-0 = <&sound_clk_pins>;
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pinctrl-names = "default";
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can0_pins: can0 {
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pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
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<RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
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};
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/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
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can0-stb-hog {
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gpio-hog;
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gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "can0_stb";
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};
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can1_pins: can1 {
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pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
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<RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
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};
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/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
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can1-stb-hog {
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gpio-hog;
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gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "can1_stb";
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};
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i2c0_pins: i2c0 {
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pins = "RIIC0_SDA", "RIIC0_SCL";
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input-enable;
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};
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i2c1_pins: i2c1 {
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pins = "RIIC1_SDA", "RIIC1_SCL";
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input-enable;
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};
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i2c3_pins: i2c3 {
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pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
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<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
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};
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mtu3_pins: mtu3 {
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mtu3-ext-clk-input-pin {
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pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
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<RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */
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};
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mtu3-pwm {
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pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
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<RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
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<RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
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<RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
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};
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#if MTU3_COUNTER_Z_PHASE_SIGNAL
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mtu3-zphase-clk {
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pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */
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};
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#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
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};
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scif0_pins: scif0 {
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pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
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<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
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};
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scif2_pins: scif2 {
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pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
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<RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
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<RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
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<RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
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};
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sd1-pwr-en-hog {
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gpio-hog;
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gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "sd1_pwr_en";
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};
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sdhi1_pins: sd1 {
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sd1_data {
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pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
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power-source = <3300>;
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};
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sd1_ctrl {
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pins = "SD1_CLK", "SD1_CMD";
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power-source = <3300>;
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};
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sd1_mux {
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pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
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};
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};
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sdhi1_pins_uhs: sd1_uhs {
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sd1_data_uhs {
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pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
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power-source = <1800>;
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};
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sd1_ctrl_uhs {
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pins = "SD1_CLK", "SD1_CMD";
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power-source = <1800>;
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};
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sd1_mux_uhs {
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pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
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};
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};
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sound_clk_pins: sound_clk {
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pins = "AUDIO_CLK1", "AUDIO_CLK2";
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input-enable;
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};
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spi1_pins: spi1 {
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pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
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<RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
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<RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
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<RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
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};
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ssi0_pins: ssi0 {
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pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
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<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
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<RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
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<RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
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};
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usb0_pins: usb0 {
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pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
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<RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
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<RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
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};
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usb1_pins: usb1 {
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pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
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<RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
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};
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};
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@ -1,371 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
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#define EMMC 1
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/*
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* To enable uSD card on CN3,
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* SW1[2] should be at position 3/ON.
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* Disable eMMC by setting "#define EMMC 0" above.
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*/
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#define SDHI (!EMMC)
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/ {
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aliases {
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ethernet0 = ð0;
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ethernet1 = ð1;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_1p1v: regulator-vdd-core {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.1V";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
states = <3300000 1>, <1800000 0>;
|
||||
regulator-boot-on;
|
||||
gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* 32.768kHz crystal */
|
||||
x2: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
pinctrl-0 = <&adc_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/delete-node/ channel@6;
|
||||
/delete-node/ channel@7;
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-0 = <ð0_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@7 {
|
||||
compatible = "ethernet-phy-id0022.1640",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <7>;
|
||||
interrupt-parent = <&irqc>;
|
||||
interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
|
||||
rxc-skew-psec = <2400>;
|
||||
txc-skew-psec = <2400>;
|
||||
rxdv-skew-psec = <0>;
|
||||
txen-skew-psec = <0>;
|
||||
rxd0-skew-psec = <0>;
|
||||
rxd1-skew-psec = <0>;
|
||||
rxd2-skew-psec = <0>;
|
||||
rxd3-skew-psec = <0>;
|
||||
txd0-skew-psec = <0>;
|
||||
txd1-skew-psec = <0>;
|
||||
txd2-skew-psec = <0>;
|
||||
txd3-skew-psec = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ð1 {
|
||||
pinctrl-0 = <ð1_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@7 {
|
||||
compatible = "ethernet-phy-id0022.1640",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <7>;
|
||||
interrupt-parent = <&irqc>;
|
||||
interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
|
||||
rxc-skew-psec = <2400>;
|
||||
txc-skew-psec = <2400>;
|
||||
rxdv-skew-psec = <0>;
|
||||
txen-skew-psec = <0>;
|
||||
rxd0-skew-psec = <0>;
|
||||
rxd1-skew-psec = <0>;
|
||||
rxd2-skew-psec = <0>;
|
||||
rxd3-skew-psec = <0>;
|
||||
txd0-skew-psec = <0>;
|
||||
txd1-skew-psec = <0>;
|
||||
txd2-skew-psec = <0>;
|
||||
txd3-skew-psec = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <®_1p1v>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
raa215300: pmic@12 {
|
||||
compatible = "renesas,raa215300";
|
||||
reg = <0x12>, <0x6f>;
|
||||
reg-names = "main", "rtc";
|
||||
|
||||
clocks = <&x2>;
|
||||
clock-names = "xin";
|
||||
};
|
||||
};
|
||||
|
||||
&ostm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
adc_pins: adc {
|
||||
pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
|
||||
};
|
||||
|
||||
eth0_pins: eth0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
|
||||
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
|
||||
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
|
||||
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
|
||||
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
|
||||
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
|
||||
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
|
||||
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
|
||||
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
|
||||
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
|
||||
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
|
||||
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
|
||||
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
|
||||
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
|
||||
<RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
|
||||
<RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
|
||||
};
|
||||
|
||||
eth1_pins: eth1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
|
||||
<RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
|
||||
<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
|
||||
<RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
|
||||
<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
|
||||
<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
|
||||
<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
|
||||
<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
|
||||
<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
|
||||
<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
|
||||
<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
|
||||
<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
|
||||
<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
|
||||
<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
|
||||
<RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
|
||||
<RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
|
||||
};
|
||||
|
||||
gpio-sd0-pwr-en-hog {
|
||||
gpio-hog;
|
||||
gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "gpio_sd0_pwr_en";
|
||||
};
|
||||
|
||||
qspi0_pins: qspi0 {
|
||||
qspi0-data {
|
||||
pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
qspi0-ctrl {
|
||||
pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
|
||||
power-source = <1800>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
|
||||
* The below switch logic can be used to select the device between
|
||||
* eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
|
||||
* SW1[2] should be at position 2/OFF to enable 64 GB eMMC
|
||||
* SW1[2] should be at position 3/ON to enable uSD card CN3
|
||||
*/
|
||||
sd0-dev-sel-hog {
|
||||
gpio-hog;
|
||||
gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "sd0_dev_sel";
|
||||
};
|
||||
|
||||
sdhi0_emmc_pins: sd0emmc {
|
||||
sd0_emmc_data {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
|
||||
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd0_emmc_ctrl {
|
||||
pins = "SD0_CLK", "SD0_CMD";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd0_emmc_rst {
|
||||
pins = "SD0_RST#";
|
||||
power-source = <1800>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
sd0_data {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sd0_ctrl {
|
||||
pins = "SD0_CLK", "SD0_CMD";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sd0_mux {
|
||||
pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
sd0_data_uhs {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd0_ctrl_uhs {
|
||||
pins = "SD0_CLK", "SD0_CMD";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd0_mux_uhs {
|
||||
pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sbc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "micron,mt25qu512a", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
m25p,fast-read;
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
boot@0 {
|
||||
reg = <0x00000000 0x2000000>;
|
||||
read-only;
|
||||
};
|
||||
user@2000000 {
|
||||
reg = <0x2000000 0x2000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#if SDHI
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
#if EMMC
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_emmc_pins>;
|
||||
pinctrl-1 = <&sdhi0_emmc_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
fixed-emmc-driver-type = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&wdt0 {
|
||||
status = "okay";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
|
||||
&wdt1 {
|
||||
status = "okay";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
|
|
@ -1,181 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial1 = &scif2;
|
||||
i2c3 = &i2c3;
|
||||
};
|
||||
|
||||
osc1: cec-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "d";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7535_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_dai {
|
||||
sound-dai = <&ssi0>;
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&adv7535_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
adv7535: hdmi@3d {
|
||||
compatible = "adi,adv7535";
|
||||
reg = <0x3d>;
|
||||
|
||||
interrupt-parent = <&pinctrl>;
|
||||
interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
|
||||
clocks = <&osc1>;
|
||||
clock-names = "cec";
|
||||
avdd-supply = <®_1p8v>;
|
||||
dvdd-supply = <®_1p8v>;
|
||||
pvdd-supply = <®_1p8v>;
|
||||
a2vdd-supply = <®_1p8v>;
|
||||
v3p3-supply = <®_3p3v>;
|
||||
v1p2-supply = <®_1p8v>;
|
||||
|
||||
adi,dsi-lanes = <4>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7535_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7535_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
wm8978: codec@1a {
|
||||
compatible = "wlf,wm8978";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x1a>;
|
||||
};
|
||||
|
||||
versa3: clock-generator@68 {
|
||||
compatible = "renesas,5p35023";
|
||||
reg = <0x68>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&x1>;
|
||||
|
||||
renesas,settings = [
|
||||
80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
|
||||
00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
|
||||
80 b0 45 c4 95
|
||||
];
|
||||
|
||||
assigned-clocks = <&versa3 0>, <&versa3 1>,
|
||||
<&versa3 2>, <&versa3 3>,
|
||||
<&versa3 4>, <&versa3 5>;
|
||||
assigned-clock-rates = <24000000>, <11289600>,
|
||||
<11289600>, <12000000>,
|
||||
<25000000>, <12288000>;
|
||||
};
|
||||
};
|
||||
|
||||
#if PMOD_MTU3
|
||||
&mtu3 {
|
||||
pinctrl-0 = <&mtu3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#if MTU3_COUNTER_Z_PHASE_SIGNAL
|
||||
/* SDHI cd pin is muxed with counter Z phase signal */
|
||||
&sdhi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
|
||||
|
||||
&spi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
#endif /* PMOD_MTU3 */
|
||||
|
||||
/*
|
||||
* To enable SCIF2 (SER0) on PMOD1 (CN7)
|
||||
* SW1 should be at position 2->3 so that SER0_CTS# line is activated
|
||||
* SW2 should be at position 2->3 so that SER0_TX line is activated
|
||||
* SW3 should be at position 2->3 so that SER0_RX line is activated
|
||||
* SW4 should be at position 2->3 so that SER0_RTS# line is activated
|
||||
*/
|
||||
#if PMOD1_SER0
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&ssi0 {
|
||||
pinctrl-0 = <&ssi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vccq_sdhi1 {
|
||||
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue