board: emcraft: Add support for Emcraft Systems NavQ+

The Emcraft Systems NavQ+ kit is a mobile robotics platform
based on NXP i.MX8 MPlus SoC.

The following interfaces and devices are enabled:
- eMMC
- Gigabit Ethernet (through eQOS interface)
- SD-Card
- UART console

The device tree file is taken from upstream Linux Kernel
through OF_UPSTREAM

Signed-off-by: Gilles Talis <gilles.talis@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

arch/arm/dts/imx8mp-navqp-u-boot.dtsi

@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019, 2021 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		bootph-pre-ram;
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
+	bootph-all;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+	bootph-all;
+};
+
+&gpio1 {
+	bootph-pre-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+};
+
+&gpio3 {
+	bootph-pre-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+};
+
+&gpio5 {
+	bootph-pre-ram;
+};
+
+&i2c1 {
+	bootph-all;
+};
+
+&pinctrl_i2c1 {
+	bootph-pre-ram;
+};
+
+&pinctrl_pmic {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart2 {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc3 {
+	bootph-pre-ram;
+};
+
+&pinctrl_wdog {
+	bootph-pre-ram;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+};
+
+&reg_usdhc2_vmmc {
+	bootph-pre-ram;
+};
+
+&uart2 {
+	bootph-pre-ram;
+};
+
+&usdhc1 {
+	bootph-pre-ram;
+};
+
+&usdhc2 {
+	bootph-pre-ram;
+};
+
+&usdhc3 {
+	bootph-pre-ram;
+};
+
+&wdog1 {
+	bootph-pre-ram;
+};

arch/arm/mach-imx/imx8m/Kconfig

@@ -228,6 +228,13 @@ config TARGET_IMX8MP_EVK
 	select SPL_CRYPTO if SPL
 	imply OF_UPSTREAM
 
+config TARGET_IMX8MP_NAVQP
+	bool "Emcraft Systems i.MX8M Plus NavQ+ board"
+	select IMX8MP
+	select IMX8M_LPDDR4
+	select SUPPORT_SPL
+	imply OF_UPSTREAM
+
 config TARGET_IMX8MP_VENICE
 	bool "Support Gateworks Venice iMX8M Plus module"
 	select IMX8MP
@@ -358,6 +365,7 @@ source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
 source "board/data_modul/imx8mm_edm_sbc/Kconfig"
 source "board/data_modul/imx8mp_edm_sbc/Kconfig"
 source "board/dhelectronics/dh_imx8mp/Kconfig"
+source "board/emcraft/imx8mp_navqp/Kconfig"
 source "board/engicam/imx8mm/Kconfig"
 source "board/engicam/imx8mp/Kconfig"
 source "board/freescale/imx8mq_evk/Kconfig"

board/emcraft/imx8mp_navqp/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_IMX8MP_NAVQP
+
+config SYS_BOARD
+	default "imx8mp_navqp"
+
+config SYS_VENDOR
+	default "emcraft"
+
+config SYS_CONFIG_NAME
+	default "imx8mp_navqp"
+
+config IMX_CONFIG
+	default "board/emcraft/imx8mp_navqp/imximage-8mp-lpddr4.cfg"
+
+endif

board/emcraft/imx8mp_navqp/MAINTAINERS

@@ -0,0 +1,8 @@
+Emcraft Systems NavQ+ board (i.MX8M Plus)
+M:	Gilles Talis <gilles.talis@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/imx8mp-navqp-u-boot.dtsi
+F:	board/emcraft/imx8mp_navqp/
+F:	configs/imx8mp_navqp_defconfig
+F:	doc/board/emcraft/
+F:	include/configs/imx8mp_navqp.h

board/emcraft/imx8mp_navqp/Makefile

@@ -0,0 +1,13 @@
+#
+# Copyright 2019 NXP
+# Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mp_navqp.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif

board/emcraft/imx8mp_navqp/imx8mp_navqp.c

@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+int board_init(void)
+{
+	return 0;
+}

board/emcraft/imx8mp_navqp/imx8mp_navqp.env

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include <config_distro_bootcmd.h>
+
+scriptaddr=CONFIG_SYS_LOAD_ADDR
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+image=Image
+console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200
+fdt_addr_r=0x43000000
+boot_fdt=try
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+initrd_addr=0x43800000
+bootm_size=0x10000000
+mmcpart=1
+mmcroot=/dev/mmcblk1p2 rootwait rw

board/emcraft/imx8mp_navqp/imximage-8mp-lpddr4.cfg

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021, 2024 NXP
+ */
+
+ROM_VERSION	v2
+BOOT_FROM	sd
+LOADER		u-boot-spl-ddr.bin	0x920000

board/emcraft/imx8mp_navqp/spl.c

@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2018-2019, 2021 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/sections.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+	/*
+	 * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
+	 * not allow to change it. Should set the clock after PMIC
+	 * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
+	 * set by ROM for ND VDD_SOC
+	 */
+	clock_enable(CCGR_GIC, 0);
+	clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+	clock_enable(CCGR_GIC, 1);
+
+	puts("Normal Boot\n");
+}
+
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pmic@25", &dev);
+	if (ret == -ENODEV) {
+		puts("Failed to get PMIC\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
+
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+	/*
+	 * Increase VDD_SOC to typical value 0.95V before first
+	 * DRAM access, set DVS1 to 0.85V for suspend.
+	 * Enable DVS control through PMIC_STBY_REQ and
+	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+	 */
+	if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+	else
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
+
+	/* Set DVS1 to 0.85v for suspend. */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+
+	/*
+	 * Enable DVS control through PMIC_STBY_REQ and
+	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
+	 */
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+	/*
+	 * Kernel uses OD/OD freq for SOC.
+	 * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD
+	 * voltage 0.95V.
+	 */
+	pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
+
+	return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	if (is_imx8mp() &&
+	    !strcmp(name, "imx8mp-navqp"))
+		return 0;
+
+	return -EINVAL;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	preloader_console_init();
+
+	enable_tzc380();
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}

configs/imx8mp_navqp_defconfig

@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-navqp"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_NAVQP=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x98fc00
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-navqp.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_SPL_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_IMX_WATCHDOG=y

doc/board/emcraft/imx8mp-navqp.rst

@@ -0,0 +1,65 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. sectionauthor:: Gilles Talis <gilles.talis@gmail.com>
+
+i.MX8M Plus NavQ+ Board
+=======================
+
+U-Boot for the EmCraft Systems i.MX8M Plus NavQ+ board
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get the DDR firmware
+- Build U-Boot
+- Flash to eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware (Trusted Firmware A)
+-----------------------------------------------------------
+
+.. code-block:: bash
+
+    $ echo "Downloading and building TF-A..."
+    $ git clone -b lts-v2.10 https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+    $ cd trusted-firmware-a
+
+Then build ATF (TF-A):
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-linux-gnu-
+    $ make PLAT=imx8mp bl31
+    $ cp build/imx8mp/release/bl31.bin ../
+
+Get the DDR Firmware
+--------------------
+
+.. code-block:: bash
+
+    $ cd ..
+    $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.23.bin
+    $ chmod +x firmware-imx-8.23.bin
+    $ ./firmware-imx-8.23.bin
+    $ cp firmware-imx-8.23/firmware/ddr/synopsys/lpddr4*_202006.bin ./
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-linux-gnu-
+    $ make imx8mp_navqp_defconfig
+    $ make
+
+Burn the flash.bin to the MicroSD card at offset 32KB:
+
+.. code-block:: bash
+
+   $ sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
+
+Boot
+----
+
+Set Boot switch to SD boot
+Use /dev/ttyUSB0 for U-Boot console

doc/board/emcraft/index.rst

@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Emcraft
+=======
+
+.. toctree::
+   :maxdepth: 2
+
+   imx8mp-navqp

doc/board/index.rst

@@ -24,6 +24,7 @@ Board-specific doc
    cloos/index
    congatec/index
    coreboot/index
+   emcraft/index
    emulation/index
    gateworks/index
    google/index

include/configs/imx8mp_navqp.h

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#ifndef __IMX8MP_NAVQP_H
+#define __IMX8MP_NAVQP_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CFG_EXTRA_ENV_SETTINGS \
+	BOOTENV
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	0x80000
+
+/* 8GB DDR */
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0xC0000000	/* 3 GB */
+#define PHYS_SDRAM_2			0x100000000
+#define PHYS_SDRAM_2_SIZE		0x140000000	/* 5 GB */
+
+#endif