mirror of
https://github.com/u-boot/u-boot.git
synced 2025-04-15 17:34:43 +00:00
Subtree merge tag 'v6.13-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git [rockchip fixes from Jonas Karlman via IRC]
This commit is contained in:
Tom Rini
commit
d8a7100d65
1500 changed files with 78946 additions and 23391 deletions
|
|
@ -146,6 +146,10 @@
|
|||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&xin24m {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
|
||||
&binman {
|
||||
simple-bin-spi {
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk356x.dtsi"
|
||||
#include "rk356x-base.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Generic RK3566/RK3568";
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))
|
|||
override DTC_FLAGS := \
|
||||
-Wno-avoid_unnecessary_addr_size \
|
||||
-Wno-graph_child_address \
|
||||
-Wno-interrupt_provider \
|
||||
-Wno-unique_unit_address \
|
||||
-Wunique_unit_address_if_enabled
|
||||
|
||||
|
|
|
|||
42
dts/upstream/Bindings/arm/airoha,en7581-chip-scu.yaml
Normal file
42
dts/upstream/Bindings/arm/airoha,en7581-chip-scu.yaml
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/airoha,en7581-chip-scu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Airoha Chip SCU Controller for EN7581 SoC
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
|
||||
description:
|
||||
The airoha chip-scu block provides a configuration interface for clock,
|
||||
io-muxing and other functionalities used by multiple controllers (e.g. clock,
|
||||
pinctrl, ecc) on EN7581 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- airoha,en7581-chip-scu
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
syscon@1fa20000 {
|
||||
compatible = "airoha,en7581-chip-scu", "syscon";
|
||||
reg = <0x0 0x1fa20000 0x0 0x388>;
|
||||
};
|
||||
};
|
||||
|
|
@ -12,7 +12,58 @@ maintainers:
|
|||
description: |
|
||||
ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
|
||||
|
||||
This currently includes devices based on the "M1" SoC:
|
||||
This currently includes devices based on the "A7" SoC:
|
||||
|
||||
- iPhone 5s
|
||||
- iPad Air (1)
|
||||
- iPad mini 2
|
||||
- iPad mini 3
|
||||
|
||||
Devices based on the "A8" SoC:
|
||||
|
||||
- iPhone 6
|
||||
- iPhone 6 Plus
|
||||
- iPad mini 4
|
||||
- iPod touch 6
|
||||
- Apple TV HD
|
||||
|
||||
Device based on the "A8X" SoC:
|
||||
|
||||
- iPad Air 2
|
||||
|
||||
Devices based on the "A9" SoC:
|
||||
|
||||
- iPhone 6s
|
||||
- iPhone 6s Plus
|
||||
- iPhone SE (2016)
|
||||
- iPad 5
|
||||
|
||||
Devices based on the "A9X" SoC:
|
||||
|
||||
- iPad Pro (9.7-inch)
|
||||
- iPad Pro (12.9-inch)
|
||||
|
||||
Devices based on the "A10" SoC:
|
||||
|
||||
- iPhone 7
|
||||
- iPhone 7 Plus
|
||||
- iPod touch 7
|
||||
- iPad 6
|
||||
- iPad 7
|
||||
|
||||
Devices based on the "A10X" SoC:
|
||||
|
||||
- Apple TV 4K (1st generation)
|
||||
- iPad Pro (2nd Generation) (10.5 Inch)
|
||||
- iPad Pro (2nd Generation) (12.9 Inch)
|
||||
|
||||
Devices based on the "A11" SoC:
|
||||
|
||||
- iPhone 8
|
||||
- iPhone 8 Plus
|
||||
- iPhone X
|
||||
|
||||
Devices based on the "M1" SoC:
|
||||
|
||||
- Mac mini (M1, 2020)
|
||||
- MacBook Pro (13-inch, M1, 2020)
|
||||
|
|
@ -65,6 +116,113 @@ properties:
|
|||
const: "/"
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Apple A7 SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j71 # iPad Air (Wi-Fi)
|
||||
- apple,j72 # iPad Air (Cellular)
|
||||
- apple,j73 # iPad Air (Cellular, China)
|
||||
- apple,j85 # iPad mini 2 (Wi-Fi)
|
||||
- apple,j85m # iPad mini 3 (Wi-Fi)
|
||||
- apple,j86 # iPad mini 2 (Cellular)
|
||||
- apple,j86m # iPad mini 3 (Cellular)
|
||||
- apple,j87 # iPad mini 2 (Cellular, China)
|
||||
- apple,j87m # iPad mini 3 (Cellular, China)
|
||||
- apple,n51 # iPhone 5s (GSM)
|
||||
- apple,n53 # iPhone 5s (LTE)
|
||||
- const: apple,s5l8960x
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple A8 SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j42d # Apple TV HD
|
||||
- apple,j96 # iPad mini 4 (Wi-Fi)
|
||||
- apple,j97 # iPad mini 4 (Cellular)
|
||||
- apple,n56 # iPhone 6 Plus
|
||||
- apple,n61 # iPhone 6
|
||||
- apple,n102 # iPod touch 6
|
||||
- const: apple,t7000
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple A8X SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j81 # iPad Air 2 (Wi-Fi)
|
||||
- apple,j82 # iPad Air 2 (Cellular)
|
||||
- const: apple,t7001
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple Samsung A9 SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j71s # iPad 5 (Wi-Fi) (S8000)
|
||||
- apple,j72s # iPad 5 (Cellular) (S8000)
|
||||
- apple,n66 # iPhone 6s Plus (S8000)
|
||||
- apple,n69u # iPhone SE (S8000)
|
||||
- apple,n71 # iPhone 6S (S8000)
|
||||
- const: apple,s8000
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple TSMC A9 SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j71t # iPad 5 (Wi-Fi) (S8003)
|
||||
- apple,j72t # iPad 5 (Cellular) (S8003)
|
||||
- apple,n66m # iPhone 6s Plus (S8003)
|
||||
- apple,n69 # iPhone SE (S8003)
|
||||
- apple,n71m # iPhone 6S (S8003)
|
||||
- const: apple,s8003
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple A9X SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j127 # iPad Pro (9.7-inch) (Wi-Fi)
|
||||
- apple,j128 # iPad Pro (9.7-inch) (Cellular)
|
||||
- apple,j98a # iPad Pro (12.9-inch) (Wi-Fi)
|
||||
- apple,j99a # iPad Pro (12.9-inch) (Cellular)
|
||||
- const: apple,s8001
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple A10 SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,d10 # iPhone 7 (Qualcomm)
|
||||
- apple,d11 # iPhone 7 (Intel)
|
||||
- apple,d101 # iPhone 7 Plus (Qualcomm)
|
||||
- apple,d111 # iPhone 7 Plus (Intel)
|
||||
- apple,j71b # iPad 6 (Wi-Fi)
|
||||
- apple,j72b # iPad 6 (Cellular)
|
||||
- apple,j171 # iPad 7 (Wi-Fi)
|
||||
- apple,j172 # iPad 7 (Cellular)
|
||||
- apple,n112 # iPod touch 7
|
||||
- const: apple,t8010
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple A10X SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j105a # Apple TV 4K (1st Generation)
|
||||
- apple,j120 # iPad Pro 2 (12.9-inch) (Wi-Fi)
|
||||
- apple,j121 # iPad Pro 2 (12.9-inch) (Cellular)
|
||||
- apple,j207 # iPad Pro 2 (10.5-inch) (Wi-Fi)
|
||||
- apple,j208 # iPad Pro 2 (10.5-inch) (Cellular)
|
||||
- const: apple,t8011
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple A11 SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,d20 # iPhone 8 (Global)
|
||||
- apple,d21 # iPhone 8 Plus (Global)
|
||||
- apple,d22 # iPhone X (Global)
|
||||
- apple,d201 # iPhone 8 (GSM)
|
||||
- apple,d211 # iPhone 8 Plus (GSM)
|
||||
- apple,d221 # iPhone X (GSM)
|
||||
- const: apple,t8015
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple M1 SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -106,6 +106,12 @@ properties:
|
|||
- const: microchip,sam9x60
|
||||
- const: atmel,at91sam9
|
||||
|
||||
- description: Microchip SAM9X7 Evaluation Boards
|
||||
items:
|
||||
- const: microchip,sam9x75-curiosity
|
||||
- const: microchip,sam9x7
|
||||
- const: atmel,at91sam9
|
||||
|
||||
- description: Nattis v2 board with Natte v2 power board
|
||||
items:
|
||||
- const: axentia,nattis-2
|
||||
|
|
|
|||
|
|
@ -87,8 +87,14 @@ properties:
|
|||
enum:
|
||||
- apple,avalanche
|
||||
- apple,blizzard
|
||||
- apple,icestorm
|
||||
- apple,cyclone
|
||||
- apple,firestorm
|
||||
- apple,hurricane-zephyr
|
||||
- apple,icestorm
|
||||
- apple,mistral
|
||||
- apple,monsoon
|
||||
- apple,twister
|
||||
- apple,typhoon
|
||||
- arm,arm710t
|
||||
- arm,arm720t
|
||||
- arm,arm740t
|
||||
|
|
@ -202,10 +208,14 @@ properties:
|
|||
- qcom,kryo560
|
||||
- qcom,kryo570
|
||||
- qcom,kryo660
|
||||
- qcom,kryo670
|
||||
- qcom,kryo685
|
||||
- qcom,kryo780
|
||||
- qcom,oryon
|
||||
- qcom,scorpion
|
||||
- samsung,mongoose-m2
|
||||
- samsung,mongoose-m3
|
||||
- samsung,mongoose-m5
|
||||
|
||||
enable-method:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
|
|
|
|||
|
|
@ -379,7 +379,9 @@ properties:
|
|||
|
||||
- description: i.MX6Q PHYTEC phyFLEX-i.MX6
|
||||
items:
|
||||
- const: phytec,imx6q-pbab01 # PHYTEC phyFLEX carrier board
|
||||
- enum:
|
||||
- comvetia,imx6q-lxr # Comvetia LXR board
|
||||
- phytec,imx6q-pbab01 # PHYTEC phyFLEX carrier board
|
||||
- const: phytec,imx6q-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
|
||||
- const: fsl,imx6q
|
||||
|
||||
|
|
@ -523,9 +525,11 @@ properties:
|
|||
- const: dfi,fs700e-m60
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6DL DHCOM PicoITX Board
|
||||
- description: i.MX6DL DHCOM based Boards
|
||||
items:
|
||||
- const: dh,imx6dl-dhcom-picoitx
|
||||
- enum:
|
||||
- dh,imx6dl-dhcom-pdk2 # i.MX6DL DHCOM SoM on PDK2 board
|
||||
- dh,imx6dl-dhcom-picoitx # i.MX6DL DHCOM SoM on PicoITX board
|
||||
- const: dh,imx6dl-dhcom-som
|
||||
- const: fsl,imx6dl
|
||||
|
||||
|
|
@ -620,6 +624,14 @@ properties:
|
|||
- kobo,librah2o
|
||||
- const: fsl,imx6sll
|
||||
|
||||
- description: i.MX6SLL Kobo Clara 2e Rev. A/B
|
||||
items:
|
||||
- enum:
|
||||
- kobo,clara2e-a
|
||||
- kobo,clara2e-b
|
||||
- const: kobo,clara2e
|
||||
- const: fsl,imx6sll
|
||||
|
||||
- description: i.MX6SX based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -995,6 +1007,7 @@ properties:
|
|||
- menlo,mx8menlo # Verdin iMX8M Mini Module on i.MX8MM Menlo board
|
||||
- toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
|
||||
- toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board
|
||||
- toradex,verdin-imx8mm-nonwifi-ivy # Verdin iMX8M Mini Module on Ivy
|
||||
- toradex,verdin-imx8mm-nonwifi-mallow # Verdin iMX8M Mini Module on Mallow
|
||||
- toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia
|
||||
- const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
|
||||
|
|
@ -1006,6 +1019,7 @@ properties:
|
|||
- enum:
|
||||
- toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
|
||||
- toradex,verdin-imx8mm-wifi-ivy # Verdin iMX8M Mini Wi-Fi / BT Module on Ivy
|
||||
- toradex,verdin-imx8mm-wifi-mallow # Verdin iMX8M Mini Wi-Fi / BT Module on Mallow
|
||||
- toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia
|
||||
- const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
|
||||
|
|
@ -1082,12 +1096,14 @@ properties:
|
|||
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
|
||||
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
|
||||
- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
|
||||
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
|
||||
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
|
||||
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
|
||||
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
|
||||
- ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Avnet (MSC Branded) Boards with SM2S i.MX8M Plus Modules
|
||||
|
|
@ -1097,11 +1113,19 @@ properties:
|
|||
- const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Boundary Device Nitrogen8MP Universal SMARC Carrier Board
|
||||
items:
|
||||
- const: boundary,imx8mp-nitrogen-smarc-universal-board
|
||||
- const: boundary,imx8mp-nitrogen-smarc-som
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: i.MX8MP DHCOM based Boards
|
||||
items:
|
||||
- enum:
|
||||
- dh,imx8mp-dhcom-drc02 # i.MX8MP DHCOM SoM on DRC02 board
|
||||
- dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board
|
||||
- dh,imx8mp-dhcom-pdk3 # i.MX8MP DHCOM SoM on PDK3 board
|
||||
- dh,imx8mp-dhcom-picoitx # i.MX8MP DHCOM SoM on PicoITX board
|
||||
- const: dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
|
|
@ -1112,6 +1136,19 @@ properties:
|
|||
- const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Kontron i.MX8MP OSM-S SoM based Boards
|
||||
items:
|
||||
- const: kontron,imx8mp-bl-osm-s # Kontron BL i.MX8MP OSM-S Board
|
||||
- const: kontron,imx8mp-osm-s # Kontron i.MX8MP OSM-S SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Kontron i.MX8MP SMARC based Boards
|
||||
items:
|
||||
- const: kontron,imx8mp-smarc-eval-carrier # Kontron i.MX8MP SMARC Eval Carrier
|
||||
- const: kontron,imx8mp-smarc # Kontron i.MX8MP SMARC Module
|
||||
- const: kontron,imx8mp-osm-s # Kontron i.MX8MP OSM-S SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: PHYTEC phyCORE-i.MX8MP SoM based boards
|
||||
items:
|
||||
- const: phytec,imx8mp-phyboard-pollux-rdk # phyBOARD-Pollux RDK
|
||||
|
|
@ -1137,6 +1174,7 @@ properties:
|
|||
- enum:
|
||||
- toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
|
||||
- toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board
|
||||
- toradex,verdin-imx8mp-nonwifi-ivy # Verdin iMX8M Plus Module on Ivy
|
||||
- toradex,verdin-imx8mp-nonwifi-mallow # Verdin iMX8M Plus Module on Mallow
|
||||
- toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia
|
||||
- const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
|
||||
|
|
@ -1148,6 +1186,7 @@ properties:
|
|||
- enum:
|
||||
- toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
|
||||
- toradex,verdin-imx8mp-wifi-ivy # Verdin iMX8M Plus Wi-Fi / BT Module on Ivy
|
||||
- toradex,verdin-imx8mp-wifi-mallow # Verdin iMX8M Plus Wi-Fi / BT Module on Mallow
|
||||
- toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia
|
||||
- const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
|
||||
|
|
|
|||
|
|
@ -93,6 +93,34 @@ properties:
|
|||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Output port node. This port connects the MMSYS/VDOSYS output to
|
||||
the first component of one display pipeline, for example one of
|
||||
the available OVL or RDMA blocks.
|
||||
Some MediaTek SoCs support multiple display outputs per MMSYS.
|
||||
properties:
|
||||
endpoint@0:
|
||||
$ref: /schemas/graph.yaml#/properties/endpoint
|
||||
description: Output to the primary display pipeline
|
||||
|
||||
endpoint@1:
|
||||
$ref: /schemas/graph.yaml#/properties/endpoint
|
||||
description: Output to the secondary display pipeline
|
||||
|
||||
endpoint@2:
|
||||
$ref: /schemas/graph.yaml#/properties/endpoint
|
||||
description: Output to the tertiary display pipeline
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- endpoint@0
|
||||
- required:
|
||||
- endpoint@1
|
||||
- required:
|
||||
- endpoint@2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ properties:
|
|||
- qcom,krait-pmu
|
||||
- qcom,scorpion-pmu
|
||||
- qcom,scorpion-mp-pmu
|
||||
- samsung,mongoose-pmu
|
||||
|
||||
interrupts:
|
||||
# Don't know how many CPUs, so no constraints to specify
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@ description: |
|
|||
qcs8550
|
||||
qcm2290
|
||||
qcm6490
|
||||
qcs9100
|
||||
qdu1000
|
||||
qrb2210
|
||||
qrb4210
|
||||
|
|
@ -76,6 +77,7 @@ description: |
|
|||
sm6375
|
||||
sm7125
|
||||
sm7225
|
||||
sm7325
|
||||
sm8150
|
||||
sm8250
|
||||
sm8350
|
||||
|
|
@ -821,6 +823,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- lenovo,thinkpad-x13s
|
||||
- microsoft,arcata
|
||||
- qcom,sc8280xp-crd
|
||||
- qcom,sc8280xp-qrd
|
||||
- const: qcom,sc8280xp
|
||||
|
|
@ -912,6 +915,13 @@ properties:
|
|||
- qcom,sa8775p-ride-r3
|
||||
- const: qcom,sa8775p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs9100-ride
|
||||
- qcom,qcs9100-ride-r3
|
||||
- const: qcom,qcs9100
|
||||
- const: qcom,sa8775p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- google,cheza
|
||||
|
|
@ -989,6 +999,11 @@ properties:
|
|||
- fairphone,fp4
|
||||
- const: qcom,sm7225
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- nothing,spacewar
|
||||
- const: qcom,sm7325
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- microsoft,surface-duo
|
||||
|
|
@ -1058,6 +1073,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- asus,vivobook-s15
|
||||
- dell,xps13-9345
|
||||
- lenovo,yoga-slim7x
|
||||
- microsoft,romulus13
|
||||
- microsoft,romulus15
|
||||
|
|
|
|||
|
|
@ -49,11 +49,23 @@ properties:
|
|||
- anbernic,rg-arc-s
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: ArmSoM Sige5 board
|
||||
items:
|
||||
- const: armsom,sige5
|
||||
- const: rockchip,rk3576
|
||||
|
||||
- description: ArmSoM Sige7 board
|
||||
items:
|
||||
- const: armsom,sige7
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: ArmSoM LM7 SoM
|
||||
items:
|
||||
- enum:
|
||||
- armsom,w3
|
||||
- const: armsom,lm7
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Asus Tinker board
|
||||
items:
|
||||
- const: asus,rk3288-tinker
|
||||
|
|
@ -232,6 +244,11 @@ properties:
|
|||
- friendlyarm,nanopi-r2s-plus
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: FriendlyElec NanoPi R3S
|
||||
items:
|
||||
- const: friendlyarm,nanopi-r3s
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: FriendlyElec NanoPi4 series boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -760,6 +777,7 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- powkiddy,rgb10max3
|
||||
- powkiddy,rgb20sx
|
||||
- powkiddy,rgb30
|
||||
- powkiddy,rk2023
|
||||
- powkiddy,x55
|
||||
|
|
@ -789,6 +807,11 @@ properties:
|
|||
- const: radxa,cm3i
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Radxa E20C
|
||||
items:
|
||||
- const: radxa,e20c
|
||||
- const: rockchip,rk3528
|
||||
|
||||
- description: Radxa Rock
|
||||
items:
|
||||
- const: radxa,rock
|
||||
|
|
@ -872,6 +895,11 @@ properties:
|
|||
- const: radxa,rock-5b
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Radxa ROCK 5C
|
||||
items:
|
||||
- const: radxa,rock-5c
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Radxa ROCK S0
|
||||
items:
|
||||
- const: radxa,rock-s0
|
||||
|
|
@ -884,6 +912,11 @@ properties:
|
|||
- radxa,zero-3w
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Relfor SAIB board
|
||||
items:
|
||||
- const: relfor,saib
|
||||
- const: rockchip,rv1109
|
||||
|
||||
- description: Rikomagic MK808 v1
|
||||
items:
|
||||
- const: rikomagic,mk808
|
||||
|
|
@ -978,6 +1011,11 @@ properties:
|
|||
- const: rockchip,rk3588-evb1-v10
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Rockchip RK3588S Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3588s-evb1-v10
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Rockchip RV1108 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rv1108-evb
|
||||
|
|
@ -1051,7 +1089,9 @@ properties:
|
|||
|
||||
- description: Xunlong Orange Pi 5
|
||||
items:
|
||||
- const: xunlong,orangepi-5
|
||||
- enum:
|
||||
- xunlong,orangepi-5
|
||||
- xunlong,orangepi-5b
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Zkmagic A95X Z2
|
||||
|
|
@ -1069,6 +1109,11 @@ properties:
|
|||
- const: rockchip,rk3568-evb1-v10
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Sinovoip RK3308 Banana Pi P2 Pro
|
||||
items:
|
||||
- const: sinovoip,rk3308-bpi-p2pro
|
||||
- const: rockchip,rk3308
|
||||
|
||||
- description: Sinovoip RK3568 Banana Pi R2 Pro
|
||||
items:
|
||||
- const: sinovoip,rk3568-bpi-r2pro
|
||||
|
|
|
|||
|
|
@ -224,6 +224,24 @@ properties:
|
|||
- winlink,e850-96 # WinLink E850-96
|
||||
- const: samsung,exynos850
|
||||
|
||||
- description: Exynos8895 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,dreamlte # Samsung Galaxy S8 (SM-G950F)
|
||||
- const: samsung,exynos8895
|
||||
|
||||
- description: Exynos9810 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,starlte # Samsung Galaxy S9 (SM-G960F)
|
||||
- const: samsung,exynos9810
|
||||
|
||||
- description: Exynos990 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,c1s # Samsung Galaxy Note20 5G (SM-N981B)
|
||||
- const: samsung,exynos990
|
||||
|
||||
- description: Exynos Auto v9 based boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -846,6 +846,12 @@ properties:
|
|||
- const: allwinner,sun50i-h64
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: RerVision A33-Vstar (with A33-Core1 SoM)
|
||||
items:
|
||||
- const: rervision,a33-vstar
|
||||
- const: rervision,a33-core1
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: RerVision H3-DVK
|
||||
items:
|
||||
- const: rervision,h3-dvk
|
||||
|
|
|
|||
|
|
@ -217,6 +217,11 @@ properties:
|
|||
- const: nvidia,p3737-0000+p3701-0000
|
||||
- const: nvidia,p3701-0000
|
||||
- const: nvidia,tegra234
|
||||
- description: Jetson AGX Orin Developer Kit with Industrial Module
|
||||
items:
|
||||
- const: nvidia,p3737-0000+p3701-0008
|
||||
- const: nvidia,p3701-0008
|
||||
- const: nvidia,tegra234
|
||||
- description: NVIDIA IGX Orin Development Kit
|
||||
items:
|
||||
- const: nvidia,p3740-0002+p3701-0008
|
||||
|
|
|
|||
|
|
@ -56,6 +56,7 @@ properties:
|
|||
- enum:
|
||||
- toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia
|
||||
- toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board
|
||||
- toradex,verdin-am62-nonwifi-ivy # Verdin AM62 Module on Ivy
|
||||
- toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow
|
||||
- toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia
|
||||
- const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT
|
||||
|
|
@ -67,6 +68,7 @@ properties:
|
|||
- enum:
|
||||
- toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B.
|
||||
- toradex,verdin-am62-wifi-ivy # Verdin AM62 Wi-Fi / BT Module on Ivy
|
||||
- toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow
|
||||
- toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia
|
||||
- const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module
|
||||
|
|
@ -144,6 +146,12 @@ properties:
|
|||
- ti,j722s-evm
|
||||
- const: ti,j722s
|
||||
|
||||
- description: K3 J742S2 SoC
|
||||
items:
|
||||
- enum:
|
||||
- ti,j742s2-evm
|
||||
- const: ti,j742s2
|
||||
|
||||
- description: K3 J784s4 SoC
|
||||
items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -84,6 +84,9 @@ properties:
|
|||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"^sata-port@[0-9a-f]+$":
|
||||
$ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
|
||||
|
|
|
|||
5
dts/upstream/Bindings/cache/l2c2x0.yaml
vendored
5
dts/upstream/Bindings/cache/l2c2x0.yaml
vendored
|
|
@ -100,9 +100,8 @@ properties:
|
|||
filter. Addresses in the filter window are directed to the M1 port. Other
|
||||
addresses will go to the M0 port.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
arm,io-coherent:
|
||||
description: indicates that the system is operating in an hardware
|
||||
|
|
|
|||
70
dts/upstream/Bindings/cache/qcom,llcc.yaml
vendored
70
dts/upstream/Bindings/cache/qcom,llcc.yaml
vendored
|
|
@ -20,8 +20,12 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qcs615-llcc
|
||||
- qcom,qcs8300-llcc
|
||||
- qcom,qdu1000-llcc
|
||||
- qcom,sa8775p-llcc
|
||||
- qcom,sar1130p-llcc
|
||||
- qcom,sar2130p-llcc
|
||||
- qcom,sc7180-llcc
|
||||
- qcom,sc7280-llcc
|
||||
- qcom,sc8180x-llcc
|
||||
|
|
@ -39,11 +43,11 @@ properties:
|
|||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 9
|
||||
maxItems: 10
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
maxItems: 9
|
||||
maxItems: 10
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
|
@ -67,6 +71,33 @@ allOf:
|
|||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sar1130p-llcc
|
||||
- qcom,sar2130p-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC0 base register region
|
||||
- description: LLCC1 base register region
|
||||
- description: LLCC broadcast OR register region
|
||||
- description: LLCC broadcast AND register region
|
||||
- description: LLCC scratchpad broadcast OR register region
|
||||
- description: LLCC scratchpad broadcast AND register region
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
- const: llcc1_base
|
||||
- const: llcc_broadcast_base
|
||||
- const: llcc_broadcast_and_base
|
||||
- const: llcc_scratchpad_broadcast_base
|
||||
- const: llcc_scratchpad_broadcast_and_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,qcs615-llcc
|
||||
- qcom,sc7180-llcc
|
||||
- qcom,sm6350-llcc
|
||||
then:
|
||||
|
|
@ -134,7 +165,6 @@ allOf:
|
|||
- qcom,qdu1000-llcc
|
||||
- qcom,sc8180x-llcc
|
||||
- qcom,sc8280xp-llcc
|
||||
- qcom,x1e80100-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
|
|
@ -165,6 +195,40 @@ allOf:
|
|||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,x1e80100-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC0 base register region
|
||||
- description: LLCC1 base register region
|
||||
- description: LLCC2 base register region
|
||||
- description: LLCC3 base register region
|
||||
- description: LLCC4 base register region
|
||||
- description: LLCC5 base register region
|
||||
- description: LLCC6 base register region
|
||||
- description: LLCC7 base register region
|
||||
- description: LLCC broadcast base register region
|
||||
- description: LLCC broadcast AND register region
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
- const: llcc1_base
|
||||
- const: llcc2_base
|
||||
- const: llcc3_base
|
||||
- const: llcc4_base
|
||||
- const: llcc5_base
|
||||
- const: llcc6_base
|
||||
- const: llcc7_base
|
||||
- const: llcc_broadcast_base
|
||||
- const: llcc_broadcast_and_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,qcs8300-llcc
|
||||
- qcom,sdm845-llcc
|
||||
- qcom,sm8150-llcc
|
||||
- qcom,sm8250-llcc
|
||||
|
|
|
|||
|
|
@ -1,52 +0,0 @@
|
|||
* Actions Semi Owl Clock Management Unit (CMU)
|
||||
|
||||
The Actions Semi Owl Clock Management Unit generates and supplies clock
|
||||
to various controllers within the SoC. The clock binding described here is
|
||||
applicable to S900, S700 and S500 SoC's.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following,
|
||||
"actions,s900-cmu"
|
||||
"actions,s700-cmu"
|
||||
"actions,s500-cmu"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- clocks: Reference to the parent clocks ("hosc", "losc")
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier, and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All available clocks are defined as preprocessor macros in corresponding
|
||||
dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or
|
||||
actions,s500-cmu.h header and can be used in device tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
The hosc clock used as input for the plls is generated outside the SoC. It is
|
||||
expected that it is defined using standard clock bindings as "hosc".
|
||||
|
||||
Actions Semi S900 CMU also requires one more clock:
|
||||
- "losc" - internal low frequency oscillator
|
||||
|
||||
Example: Clock Management Unit node:
|
||||
|
||||
cmu: clock-controller@e0160000 {
|
||||
compatible = "actions,s900-cmu";
|
||||
reg = <0x0 0xe0160000 0x0 0x1000>;
|
||||
clocks = <&hosc>, <&losc>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes clock generated by the clock
|
||||
management unit:
|
||||
|
||||
uart: serial@e012a000 {
|
||||
compatible = "actions,s900-uart", "actions,owl-uart";
|
||||
reg = <0x0 0xe012a000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu CLK_UART5>;
|
||||
};
|
||||
60
dts/upstream/Bindings/clock/actions,owl-cmu.yaml
Normal file
60
dts/upstream/Bindings/clock/actions,owl-cmu.yaml
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/actions,owl-cmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Actions Semi Owl Clock Management Unit (CMU)
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description: |
|
||||
The Actions Semi Owl Clock Management Unit generates and supplies clock
|
||||
to various controllers within the SoC.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/actions,s500-cmu.h
|
||||
include/dt-bindings/clock/actions,s700-cmu.h
|
||||
include/dt-bindings/clock/actions,s900-cmu.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- actions,s500-cmu
|
||||
- actions,s700-cmu
|
||||
- actions,s900-cmu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Host oscillator source
|
||||
- description: Internal low frequency oscillator source
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@e0160000 {
|
||||
compatible = "actions,s900-cmu";
|
||||
reg = <0xe0160000 0x1000>;
|
||||
clocks = <&hosc>, <&losc>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -26,9 +26,21 @@ properties:
|
|||
description:
|
||||
Specifies the reference clock(s) from which the output frequency is
|
||||
derived. This must either reference one clock if only the first clock
|
||||
input is connected or two if both clock inputs are connected.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
input is connected or two if both clock inputs are connected. The last
|
||||
clock is the AXI bus clock that needs to be enabled so we can access the
|
||||
core registers.
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: clkin1
|
||||
- const: s_axi_aclk
|
||||
- items:
|
||||
- const: clkin1
|
||||
- const: clkin2
|
||||
- const: s_axi_aclk
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
|
@ -40,6 +52,7 @@ required:
|
|||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -50,5 +63,6 @@ examples:
|
|||
compatible = "adi,axi-clkgen-2.00.a";
|
||||
#clock-cells = <0>;
|
||||
reg = <0xff000000 0x1000>;
|
||||
clocks = <&osc 1>;
|
||||
clocks = <&osc 1>, <&clkc 15>;
|
||||
clock-names = "clkin1", "s_axi_aclk";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -34,8 +34,10 @@ properties:
|
|||
- airoha,en7581-scu
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- description: scu base address
|
||||
- description: misc scu base address
|
||||
minItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
description:
|
||||
|
|
@ -60,9 +62,7 @@ allOf:
|
|||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: scu base address
|
||||
- description: misc scu base address
|
||||
minItems: 2
|
||||
|
||||
'#reset-cells': false
|
||||
|
||||
|
|
@ -73,11 +73,7 @@ allOf:
|
|||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: scu base address
|
||||
- description: misc scu base address
|
||||
- description: reset base address
|
||||
- description: pb scu base address
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
@ -96,12 +92,9 @@ examples:
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
scuclk: clock-controller@1fa20000 {
|
||||
scuclk: clock-controller@1fb00000 {
|
||||
compatible = "airoha,en7581-scu";
|
||||
reg = <0x0 0x1fa20000 0x0 0x400>,
|
||||
<0x0 0x1fb00000 0x0 0x90>,
|
||||
<0x0 0x1fb00830 0x0 0x8>,
|
||||
<0x0 0x1fbe3400 0x0 0xfc>;
|
||||
reg = <0x0 0x1fb00000 0x0 0x970>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
|
|||
45
dts/upstream/Bindings/clock/amlogic,meson8-clkc.yaml
Normal file
45
dts/upstream/Bindings/clock/amlogic,meson8-clkc.yaml
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/amlogic,meson8-clkc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- amlogic,meson8-clkc
|
||||
- amlogic,meson8b-clkc
|
||||
- items:
|
||||
- const: amlogic,meson8m2-clkc
|
||||
- const: amlogic,meson8-clkc
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: xtal
|
||||
- const: ddr_pll
|
||||
- const: clk_32k
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
|
||||
|
||||
The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
|
||||
supplies clock to various controllers within the SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: must be one of:
|
||||
- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
|
||||
- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
|
||||
- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
- clocks: list of clock phandles, one for each entry in clock-names
|
||||
- clock-names: should contain the following:
|
||||
* "xtal": the 24MHz system oscillator
|
||||
* "ddr_pll": the DDR PLL clock
|
||||
* "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
|
||||
- reg: base address and size of the HHI system control register space.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
|
||||
used in device tree sources.
|
||||
|
||||
Similarly a preprocessor macro for each reset line is defined in
|
||||
dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
|
||||
device tree sources).
|
||||
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clkc: clock-controller {
|
||||
compatible = "amlogic,meson8b-clkc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart_AO: serial@c81004c0 {
|
||||
compatible = "amlogic,meson-uart";
|
||||
reg = <0xc81004c0 0x14>;
|
||||
interrupts = <0 90 1>;
|
||||
clocks = <&clkc CLKID_CLK81>;
|
||||
};
|
||||
49
dts/upstream/Bindings/clock/gated-fixed-clock.yaml
Normal file
49
dts/upstream/Bindings/clock/gated-fixed-clock.yaml
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/gated-fixed-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Gated Fixed clock
|
||||
|
||||
maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: gated-fixed-clock
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clock-frequency: true
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
enable-gpios:
|
||||
description:
|
||||
Contains a single GPIO specifier for the GPIO that enables and disables
|
||||
the oscillator.
|
||||
maxItems: 1
|
||||
|
||||
vdd-supply:
|
||||
description: handle of the regulator that provides the supply voltage
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clock-frequency
|
||||
- vdd-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-1000000000 {
|
||||
compatible = "gated-fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
vdd-supply = <®_vdd>;
|
||||
};
|
||||
...
|
||||
|
|
@ -16,6 +16,7 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx91-ccm
|
||||
- fsl,imx93-ccm
|
||||
|
||||
reg:
|
||||
|
|
|
|||
48
dts/upstream/Bindings/clock/marvell,pxa1908.yaml
Normal file
48
dts/upstream/Bindings/clock/marvell,pxa1908.yaml
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell PXA1908 Clock Controllers
|
||||
|
||||
maintainers:
|
||||
- Duje Mihanović <duje.mihanovic@skole.hr>
|
||||
|
||||
description: |
|
||||
The PXA1908 clock subsystem generates and supplies clock to various
|
||||
controllers within the PXA1908 SoC. The PXA1908 contains numerous clock
|
||||
controller blocks, with the ones currently supported being APBC, APBCP, MPMU
|
||||
and APMU roughly corresponding to internal buses.
|
||||
|
||||
All these clock identifiers could be found in <include/dt-bindings/marvell,pxa1908.h>.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,pxa1908-apbc
|
||||
- marvell,pxa1908-apbcp
|
||||
- marvell,pxa1908-mpmu
|
||||
- marvell,pxa1908-apmu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# APMU block:
|
||||
- |
|
||||
clock-controller@d4282800 {
|
||||
compatible = "marvell,pxa1908-apmu";
|
||||
reg = <0xd4282800 0x400>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -12,7 +12,8 @@ maintainers:
|
|||
|
||||
description:
|
||||
The Mediatek apmixedsys controller provides PLLs to the system.
|
||||
The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
|
||||
The clock values can be found in <dt-bindings/clock/mt*-clk.h>
|
||||
and <dt-bindings/clock/mediatek,mt*-apmixedsys.h>.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -34,6 +35,7 @@ properties:
|
|||
- enum:
|
||||
- mediatek,mt2701-apmixedsys
|
||||
- mediatek,mt2712-apmixedsys
|
||||
- mediatek,mt6735-apmixedsys
|
||||
- mediatek,mt6765-apmixedsys
|
||||
- mediatek,mt6779-apmixed
|
||||
- mediatek,mt6795-apmixedsys
|
||||
|
|
|
|||
|
|
@ -11,9 +11,10 @@ maintainers:
|
|||
|
||||
description:
|
||||
The Mediatek infracfg controller provides various clocks and reset outputs
|
||||
to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
|
||||
and reset values in <dt-bindings/reset/mt*-reset.h> and
|
||||
<dt-bindings/reset/mt*-resets.h>.
|
||||
to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>
|
||||
and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in
|
||||
<dt-bindings/reset/mt*-reset.h>, <dt-bindings/reset/mt*-resets.h> and
|
||||
<dt-bindings/reset/mediatek,mt*-infracfg.h>.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -22,6 +23,7 @@ properties:
|
|||
- enum:
|
||||
- mediatek,mt2701-infracfg
|
||||
- mediatek,mt2712-infracfg
|
||||
- mediatek,mt6735-infracfg
|
||||
- mediatek,mt6765-infracfg
|
||||
- mediatek,mt6795-infracfg
|
||||
- mediatek,mt6779-infracfg_ao
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ properties:
|
|||
- enum:
|
||||
- mediatek,mt2701-pericfg
|
||||
- mediatek,mt2712-pericfg
|
||||
- mediatek,mt6735-pericfg
|
||||
- mediatek,mt6765-pericfg
|
||||
- mediatek,mt6795-pericfg
|
||||
- mediatek,mt7622-pericfg
|
||||
|
|
|
|||
|
|
@ -28,6 +28,10 @@ properties:
|
|||
- mediatek,mt2712-mfgcfg
|
||||
- mediatek,mt2712-vdecsys
|
||||
- mediatek,mt2712-vencsys
|
||||
- mediatek,mt6735-imgsys
|
||||
- mediatek,mt6735-mfgcfg
|
||||
- mediatek,mt6735-vdecsys
|
||||
- mediatek,mt6735-vencsys
|
||||
- mediatek,mt6765-camsys
|
||||
- mediatek,mt6765-imgsys
|
||||
- mediatek,mt6765-mipi0a
|
||||
|
|
|
|||
|
|
@ -12,7 +12,8 @@ maintainers:
|
|||
|
||||
description:
|
||||
The Mediatek topckgen controller provides various clocks to the system.
|
||||
The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
|
||||
The clock values can be found in <dt-bindings/clock/mt*-clk.h> and
|
||||
<dt-bindings/clock/mediatek,mt*-topckgen.h>.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -31,6 +32,7 @@ properties:
|
|||
- enum:
|
||||
- mediatek,mt2701-topckgen
|
||||
- mediatek,mt2712-topckgen
|
||||
- mediatek,mt6735-topckgen
|
||||
- mediatek,mt6765-topckgen
|
||||
- mediatek,mt6779-topckgen
|
||||
- mediatek,mt6795-topckgen
|
||||
|
|
|
|||
|
|
@ -16,7 +16,18 @@ description: |
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: microchip,lan966x-gck
|
||||
oneOf:
|
||||
- enum:
|
||||
- microchip,lan966x-gck
|
||||
- microchip,lan9691-gck
|
||||
- items:
|
||||
- enum:
|
||||
- microchip,lan9698-gck
|
||||
- microchip,lan9696-gck
|
||||
- microchip,lan9694-gck
|
||||
- microchip,lan9693-gck
|
||||
- microchip,lan9692-gck
|
||||
- const: microchip,lan9691-gck
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
|
|
|
|||
|
|
@ -1,51 +0,0 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mobileye EyeQ5 clock controller
|
||||
|
||||
description:
|
||||
The EyeQ5 clock controller handles 10 read-only PLLs derived from the main
|
||||
crystal clock. It also exposes one divider clock, a child of one of the PLLs.
|
||||
Its registers live in a shared region called OLB.
|
||||
|
||||
maintainers:
|
||||
- Grégory Clement <gregory.clement@bootlin.com>
|
||||
- Théo Lebrun <theo.lebrun@bootlin.com>
|
||||
- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mobileye,eyeq5-clk
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: plls
|
||||
- const: ospi
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description:
|
||||
Input parent clock to all PLLs. Expected to be the main crystal.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -13,9 +13,10 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- nxp,imx95-lvds-csr
|
||||
- nxp,imx95-display-csr
|
||||
- nxp,imx95-camera-csr
|
||||
- nxp,imx95-display-csr
|
||||
- nxp,imx95-hsio-blk-ctl
|
||||
- nxp,imx95-lvds-csr
|
||||
- nxp,imx95-netcmix-blk-ctrl
|
||||
- nxp,imx95-vpu-csr
|
||||
- const: syscon
|
||||
|
|
|
|||
|
|
@ -17,7 +17,9 @@ description: |
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm8450
|
||||
enum:
|
||||
- qcom,gcc-sm8450
|
||||
- qcom,sm8475-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -4,31 +4,35 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on IPQ5332
|
||||
title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on IPQ5332.
|
||||
domains on IPQ5332 and IPQ5424.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,gcc-ipq5332.h
|
||||
include/dt-bindings/clock/qcom,gcc-ipq5424.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,ipq5332-gcc
|
||||
enum:
|
||||
- qcom,ipq5332-gcc
|
||||
- qcom,ipq5424-gcc
|
||||
|
||||
clocks:
|
||||
minItems: 5
|
||||
items:
|
||||
- description: Board XO clock source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 2lane PHY pipe clock source
|
||||
- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
|
||||
- description: USB PCIE wrapper pipe clock source
|
||||
- description: PCIE 2-lane PHY2 pipe clock source
|
||||
- description: PCIE 2-lane PHY3 pipe clock source
|
||||
|
||||
'#power-domain-cells': false
|
||||
'#interconnect-cells':
|
||||
|
|
@ -38,6 +42,29 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,ipq5332-gcc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 5
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,ipq5424-gcc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
66
dts/upstream/Bindings/clock/qcom,qcs8300-gcc.yaml
Normal file
66
dts/upstream/Bindings/clock/qcom,qcs8300-gcc.yaml
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qcs8300-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on QCS8300
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
- Imran Shaik <quic_imrashai@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm Technologies, Inc. Global clock control module provides the clocks, resets and
|
||||
power domains on QCS8300
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,qcs8300-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,qcs8300-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 0 Pipe clock source
|
||||
- description: PCIE 1 Pipe clock source
|
||||
- description: PCIE Phy Auxiliary clock source
|
||||
- description: First EMAC controller reference clock
|
||||
- description: UFS Phy Rx symbol 0 clock source
|
||||
- description: UFS Phy Rx symbol 1 clock source
|
||||
- description: UFS Phy Tx symbol 0 clock source
|
||||
- description: USB3 Phy wrapper pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,qcs8300-gcc";
|
||||
reg = <0x00100000 0xc7018>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&pcie_0_pipe_clk>,
|
||||
<&pcie_1_pipe_clk>,
|
||||
<&pcie_phy_aux_clk>,
|
||||
<&rxc0_ref_clk>,
|
||||
<&ufs_phy_rx_symbol_0_clk>,
|
||||
<&ufs_phy_rx_symbol_1_clk>,
|
||||
<&ufs_phy_tx_symbol_0_clk>,
|
||||
<&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -19,6 +19,7 @@ properties:
|
|||
enum:
|
||||
- qcom,qdu1000-rpmh-clk
|
||||
- qcom,sa8775p-rpmh-clk
|
||||
- qcom,sar2130p-rpmh-clk
|
||||
- qcom,sc7180-rpmh-clk
|
||||
- qcom,sc7280-rpmh-clk
|
||||
- qcom,sc8180x-rpmh-clk
|
||||
|
|
|
|||
62
dts/upstream/Bindings/clock/qcom,sa8775p-camcc.yaml
Normal file
62
dts/upstream/Bindings/clock/qcom,sa8775p-camcc.yaml
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller on SA8775P
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SA8775p.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sa8775p-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Camera AHB clock from GCC
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: MMCX power domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
|
||||
clock-controller@ade0000 {
|
||||
compatible = "qcom,sa8775p-camcc";
|
||||
reg = <0x0ade0000 0x20000>;
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
power-domains = <&rpmhpd SA8775P_MMCX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
79
dts/upstream/Bindings/clock/qcom,sa8775p-dispcc.yaml
Normal file
79
dts/upstream/Bindings/clock/qcom,sa8775p-dispcc.yaml
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller on SA8775P
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SA8775P.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sa8775p-dispcc0
|
||||
- qcom,sa8775p-dispcc1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: GCC AHB clock source
|
||||
- description: Board XO source
|
||||
- description: Board XO_AO source
|
||||
- description: Sleep clock source
|
||||
- description: Link clock from DP0 PHY
|
||||
- description: VCO DIV clock from DP0 PHY
|
||||
- description: Link clock from DP1 PHY
|
||||
- description: VCO DIV clock from DP1 PHY
|
||||
- description: Byte clock from DSI0 PHY
|
||||
- description: Pixel clock from DSI0 PHY
|
||||
- description: Byte clock from DSI1 PHY
|
||||
- description: Pixel clock from DSI1 PHY
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: MMCX power domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sa8775p-dispcc0";
|
||||
reg = <0x0af00000 0x20000>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>,
|
||||
<&dp_phy0 0>,
|
||||
<&dp_phy0 1>,
|
||||
<&dp_phy1 2>,
|
||||
<&dp_phy1 3>,
|
||||
<&dsi_phy0 0>,
|
||||
<&dsi_phy0 1>,
|
||||
<&dsi_phy1 2>,
|
||||
<&dsi_phy1 3>;
|
||||
power-domains = <&rpmhpd SA8775P_MMCX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
62
dts/upstream/Bindings/clock/qcom,sa8775p-videocc.yaml
Normal file
62
dts/upstream/Bindings/clock/qcom,sa8775p-videocc.yaml
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Video Clock & Reset Controller on SA8775P
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module provides the clocks, resets and power
|
||||
domains on SA8775P.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,sa8775p-videocc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sa8775p-videocc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Video AHB clock from GCC
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep Clock source
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: MMCX power domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
|
||||
videocc: clock-controller@abf0000 {
|
||||
compatible = "qcom,sa8775p-videocc";
|
||||
reg = <0x0abf0000 0x10000>;
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
power-domains = <&rpmhpd SA8775P_MMCX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
65
dts/upstream/Bindings/clock/qcom,sar2130p-gcc.yaml
Normal file
65
dts/upstream/Bindings/clock/qcom,sar2130p-gcc.yaml
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on sar2130p
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and
|
||||
power domains on sar2130p.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sar2130p-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO reference clock
|
||||
- description: Sleep clock
|
||||
- description: PCIe 0 pipe clock
|
||||
- description: PCIe 1 pipe clock
|
||||
- description: Primary USB3 PHY wrapper pipe clock
|
||||
|
||||
protected-clocks:
|
||||
maxItems: 240
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
|
||||
gcc: clock-controller@100000 {
|
||||
compatible = "qcom,sar2130p-gcc";
|
||||
reg = <0x100000 0x1f4200>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&pcie_0_pipe_clk>,
|
||||
<&pcie_1_pipe_clk>,
|
||||
<&usb_0_ssphy>;
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -26,6 +26,7 @@ properties:
|
|||
enum:
|
||||
- qcom,sc8280xp-camcc
|
||||
- qcom,sm8450-camcc
|
||||
- qcom,sm8475-camcc
|
||||
- qcom,sm8550-camcc
|
||||
- qcom,sm8650-camcc
|
||||
- qcom,x1e80100-camcc
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ properties:
|
|||
compatible:
|
||||
enum:
|
||||
- qcom,sm8450-dispcc
|
||||
- qcom,sm8475-dispcc
|
||||
|
||||
clocks:
|
||||
minItems: 3
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ description: |
|
|||
domains on Qualcomm SoCs.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,sar2130p-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm4450-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm8450-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-gpucc.h
|
||||
|
|
@ -24,8 +25,10 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sar2130p-gpucc
|
||||
- qcom,sm4450-gpucc
|
||||
- qcom,sm8450-gpucc
|
||||
- qcom,sm8475-gpucc
|
||||
- qcom,sm8550-gpucc
|
||||
- qcom,sm8650-gpucc
|
||||
- qcom,x1e80100-gpucc
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ properties:
|
|||
compatible:
|
||||
enum:
|
||||
- qcom,sm8450-videocc
|
||||
- qcom,sm8475-videocc
|
||||
- qcom,sm8550-videocc
|
||||
- qcom,sm8650-videocc
|
||||
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sar2130p-dispcc
|
||||
- qcom,sm8550-dispcc
|
||||
- qcom,sm8650-dispcc
|
||||
- qcom,x1e80100-dispcc
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,sar2130p-tcsr
|
||||
- qcom,sm8550-tcsr
|
||||
- qcom,sm8650-tcsr
|
||||
- qcom,x1e80100-tcsr
|
||||
|
|
|
|||
84
dts/upstream/Bindings/clock/renesas,r9a08g045-vbattb.yaml
Normal file
84
dts/upstream/Bindings/clock/renesas,r9a08g045-vbattb.yaml
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Battery Backup Function (VBATTB)
|
||||
|
||||
description:
|
||||
Renesas VBATTB is an always on powered module (backed by battery) which
|
||||
controls the RTC clock (VBATTCLK), tamper detection logic and a small
|
||||
general usage memory (128B).
|
||||
|
||||
maintainers:
|
||||
- Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a08g045-vbattb
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: tamper detector interrupt
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: VBATTB module clock
|
||||
- description: RTC input clock (crystal or external clock device)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bclk
|
||||
- const: rtx
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: VBATTB module reset
|
||||
|
||||
quartz-load-femtofarads:
|
||||
description: load capacitance of the on board crystal
|
||||
enum: [ 4000, 7000, 9000, 12500 ]
|
||||
default: 4000
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- power-domains
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r9a08g045-cpg.h>
|
||||
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
clock-controller@1005c000 {
|
||||
compatible = "renesas,r9a08g045-vbattb";
|
||||
reg = <0x1005c000 0x1000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
|
||||
clock-names = "bclk", "rtx";
|
||||
assigned-clocks = <&vbattb VBATTB_MUX>;
|
||||
assigned-clock-parents = <&vbattb VBATTB_XC>;
|
||||
#clock-cells = <1>;
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A08G045_VBAT_BRESETN>;
|
||||
quartz-load-femtofarads = <12500>;
|
||||
};
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
* Rockchip RK3328 Clock and Reset Unit
|
||||
|
||||
The RK3328 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3328-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
- "hdmi_phy" - output clock of the hdmi phy pll - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: clock-controller@ff440000 {
|
||||
compatible = "rockchip,rk3328-cru";
|
||||
reg = <0x0 0xff440000 0x0 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@ff120000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff120000 0x100>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
74
dts/upstream/Bindings/clock/rockchip,rk3328-cru.yaml
Normal file
74
dts/upstream/Bindings/clock/rockchip,rk3328-cru.yaml
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3328-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3328 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3328 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
- "hdmi_phy" - output clock of the hdmi phy pll - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3328-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff440000 {
|
||||
compatible = "rockchip,rk3328-cru";
|
||||
reg = <0xff440000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
239
dts/upstream/Bindings/clock/samsung,exynos8895-clock.yaml
Normal file
239
dts/upstream/Bindings/clock/samsung,exynos8895-clock.yaml
Normal file
|
|
@ -0,0 +1,239 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos8895 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description: |
|
||||
Exynos8895 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. The root clock in that root tree
|
||||
is an external clock: OSCCLK (26 MHz). This external clock must be defined
|
||||
as a fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynos8895.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos8895-cmu-fsys0
|
||||
- samsung,exynos8895-cmu-fsys1
|
||||
- samsung,exynos8895-cmu-peric0
|
||||
- samsung,exynos8895-cmu-peric1
|
||||
- samsung,exynos8895-cmu-peris
|
||||
- samsung,exynos8895-cmu-top
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-fsys0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_FSYS0 BUS clock (from CMU_TOP)
|
||||
- description: CMU_FSYS0 DPGTC clock (from CMU_TOP)
|
||||
- description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)
|
||||
- description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)
|
||||
- description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: dpgtc
|
||||
- const: mmc
|
||||
- const: ufs
|
||||
- const: usbdrd30
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-fsys1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_FSYS1 BUS clock (from CMU_TOP)
|
||||
- description: CMU_FSYS1 PCIE clock (from CMU_TOP)
|
||||
- description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)
|
||||
- description: CMU_FSYS1 MMC_CARD clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: pcie
|
||||
- const: ufs
|
||||
- const: mmc
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-peric0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIC0 BUS clock (from CMU_TOP)
|
||||
- description: CMU_PERIC0 UART_DBG clock (from CMU_TOP)
|
||||
- description: CMU_PERIC0 USI00 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC0 USI01 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC0 USI02 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC0 USI03 clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: uart
|
||||
- const: usi0
|
||||
- const: usi1
|
||||
- const: usi2
|
||||
- const: usi3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-peric1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIC1 BUS clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 SPEEDY2 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 SPI_CAM0 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 SPI_CAM1 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 UART_BT clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI04 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI05 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI06 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI07 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI08 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI09 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI10 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI11 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI12 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI13 clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: speedy
|
||||
- const: cam0
|
||||
- const: cam1
|
||||
- const: uart
|
||||
- const: usi4
|
||||
- const: usi5
|
||||
- const: usi6
|
||||
- const: usi7
|
||||
- const: usi8
|
||||
- const: usi9
|
||||
- const: usi10
|
||||
- const: usi11
|
||||
- const: usi12
|
||||
- const: usi13
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-peris
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIS BUS clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynos8895.h>
|
||||
|
||||
cmu_fsys1: clock-controller@11400000 {
|
||||
compatible = "samsung,exynos8895-cmu-fsys1";
|
||||
reg = <0x11400000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
|
||||
<&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
|
||||
<&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
|
||||
<&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
|
||||
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -16,8 +16,8 @@ merged to this clock. The component clocks shall be of one of the
|
|||
"ti,*composite*-clock" types.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/mux.txt
|
||||
[3] Documentation/devicetree/bindings/clock/ti/divider.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
|
||||
[3] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml
|
||||
[4] Documentation/devicetree/bindings/clock/ti/gate.txt
|
||||
|
||||
Required properties:
|
||||
|
|
|
|||
|
|
@ -1,115 +0,0 @@
|
|||
Binding for TI divider clock
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped adjustable clock rate divider that does not gate and has
|
||||
only one input clock or parent. By default the value programmed into
|
||||
the register is one less than the actual divisor value. E.g:
|
||||
|
||||
register value actual divisor value
|
||||
0 1
|
||||
1 2
|
||||
2 3
|
||||
|
||||
This assumption may be modified by the following optional properties:
|
||||
|
||||
ti,index-starts-at-one - valid divisor values start at 1, not the default
|
||||
of 0. E.g:
|
||||
register value actual divisor value
|
||||
1 1
|
||||
2 2
|
||||
3 3
|
||||
|
||||
ti,index-power-of-two - valid divisor values are powers of two. E.g:
|
||||
register value actual divisor value
|
||||
0 1
|
||||
1 2
|
||||
2 4
|
||||
|
||||
Additionally an array of valid dividers may be supplied like so:
|
||||
|
||||
ti,dividers = <4>, <8>, <0>, <16>;
|
||||
|
||||
Which will map the resulting values to a divisor table by their index:
|
||||
register value actual divisor value
|
||||
0 4
|
||||
1 8
|
||||
2 <invalid divisor, skipped>
|
||||
3 16
|
||||
|
||||
Any zero value in this array means the corresponding bit-value is invalid
|
||||
and must not be used.
|
||||
|
||||
The binding must also provide the register to control the divider and
|
||||
unless the divider array is provided, min and max dividers. Optionally
|
||||
the number of bits to shift that mask, if necessary. If the shift value
|
||||
is missing it is the same as supplying a zero shift.
|
||||
|
||||
This binding can also optionally provide support to the hardware autoidle
|
||||
feature, see [2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : offset for register controlling adjustable divider
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,dividers : array of integers defining divisors
|
||||
- ti,bit-shift : number of bits to shift the divider value, defaults to 0
|
||||
- ti,min-div : min divisor for dividing the input clock rate, only
|
||||
needed if the first divisor is offset from the default value (1)
|
||||
- ti,max-div : max divisor for dividing the input clock rate, only needed
|
||||
if ti,dividers is not defined.
|
||||
- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
|
||||
only valid if ti,dividers is not defined.
|
||||
- ti,index-power-of-two : valid divisor programming must be a power of two,
|
||||
only valid if ti,dividers is not defined.
|
||||
- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
|
||||
see [2]
|
||||
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
|
||||
see [2]
|
||||
- ti,set-rate-parent : clk_set_rate is propagated to parent
|
||||
- ti,latch-bit : latch the divider value to HW, only needed if the register
|
||||
access requires this. As an example dra76x DPLL_GMAC H14 divider implements
|
||||
such behavior.
|
||||
|
||||
Examples:
|
||||
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_usb_ck>;
|
||||
ti,max-div = <127>;
|
||||
reg = <0x190>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
aess_fclk: aess_fclk@4a004528 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&abe_clk>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x528>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
|
||||
dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0134>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0a40>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
Binding for Texas Instruments interface clock.
|
||||
|
||||
This binding uses the common clock binding[1]. This clock is
|
||||
quite much similar to the basic gate-clock [2], however,
|
||||
it supports a number of additional features, including
|
||||
companion clock finding (match corresponding functional gate
|
||||
clock) and hardware autoidle enable / disable.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of:
|
||||
"ti,omap3-interface-clock" - basic OMAP3 interface clock
|
||||
"ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
|
||||
capability for waiting clock to be ready
|
||||
"ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
|
||||
handling
|
||||
"ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
|
||||
"ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
|
||||
"ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
|
||||
"ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
|
||||
handling
|
||||
- #clock-cells : from common clock binding; shall be set to 0
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : base address for the control register
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
|
||||
|
||||
Examples:
|
||||
aes1_ick: aes1_ick@48004a14 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x48004a14 0x4>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
cam_ick: cam_ick@48004f10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x48004f10 0x4>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-ssi-interface-clock";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
reg = <0x48004a10 0x4>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
Binding for TI mux clock.
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped multiplexer with multiple input clock signals or
|
||||
parents, one of which can be selected as output. This clock does not
|
||||
gate or adjust the parent rate via a divider or multiplier.
|
||||
|
||||
By default the "clocks" property lists the parents in the same order
|
||||
as they are programmed into the register. E.g:
|
||||
|
||||
clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
|
||||
|
||||
results in programming the register as follows:
|
||||
|
||||
register value selected parent clock
|
||||
0 foo_clock
|
||||
1 bar_clock
|
||||
2 baz_clock
|
||||
|
||||
Some clock controller IPs do not allow a value of zero to be programmed
|
||||
into the register, instead indexing begins at 1. The optional property
|
||||
"index-starts-at-one" modified the scheme as follows:
|
||||
|
||||
register value selected clock parent
|
||||
1 foo_clock
|
||||
2 bar_clock
|
||||
3 baz_clock
|
||||
|
||||
The binding must provide the register to control the mux. Optionally
|
||||
the number of bits to shift the control field in the register can be
|
||||
supplied. If the shift value is missing it is the same as supplying
|
||||
a zero shift.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of parent clocks
|
||||
- reg : register offset for register controlling adjustable mux
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,bit-shift : number of bits to shift the bit-mask, defaults to
|
||||
0 if not present
|
||||
- ti,index-starts-at-one : valid input select programming starts at 1, not
|
||||
zero
|
||||
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
|
||||
not supported by the composite-mux-clock subtype
|
||||
- ti,latch-bit : latch the mux value to HW, only needed if the register
|
||||
access requires this. As an example, dra7x DPLL_GMAC H14 muxing
|
||||
implements such behavior.
|
||||
|
||||
Examples:
|
||||
|
||||
sys_clkin_ck: sys_clkin_ck@4a306110 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
|
||||
reg = <0x0110>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x0108>;
|
||||
};
|
||||
|
||||
mcbsp5_mux_fck: mcbsp5_mux_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clocks = <&core_96m_fck>, <&mcbsp_clks>;
|
||||
ti,bit-shift = <4>;
|
||||
reg = <0x02d8>;
|
||||
};
|
||||
193
dts/upstream/Bindings/clock/ti/ti,divider-clock.yaml
Normal file
193
dts/upstream/Bindings/clock/ti/ti,divider-clock.yaml
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments divider clock
|
||||
|
||||
maintainers:
|
||||
- Tero Kristo <kristo@kernel.org>
|
||||
|
||||
description: |
|
||||
This clock It assumes a register-mapped adjustable clock rate divider
|
||||
that does not gate and has only one input clock or parent. By default the
|
||||
value programmed into the register is one less than the actual divisor value.
|
||||
E.g:
|
||||
|
||||
register value actual divisor value
|
||||
0 1
|
||||
1 2
|
||||
2 3
|
||||
|
||||
This assumption may be modified by the following optional properties:
|
||||
|
||||
ti,index-starts-at-one - valid divisor values start at 1, not the default
|
||||
of 0. E.g:
|
||||
register value actual divisor value
|
||||
1 1
|
||||
2 2
|
||||
3 3
|
||||
|
||||
ti,index-power-of-two - valid divisor values are powers of two. E.g:
|
||||
register value actual divisor value
|
||||
0 1
|
||||
1 2
|
||||
2 4
|
||||
|
||||
Additionally an array of valid dividers may be supplied like so:
|
||||
|
||||
ti,dividers = <4>, <8>, <0>, <16>;
|
||||
|
||||
Which will map the resulting values to a divisor table by their index:
|
||||
register value actual divisor value
|
||||
0 4
|
||||
1 8
|
||||
2 <invalid divisor, skipped>
|
||||
3 16
|
||||
|
||||
Any zero value in this array means the corresponding bit-value is invalid
|
||||
and must not be used.
|
||||
|
||||
The binding must also provide the register to control the divider and
|
||||
unless the divider array is provided, min and max dividers. Optionally
|
||||
the number of bits to shift that mask, if necessary. If the shift value
|
||||
is missing it is the same as supplying a zero shift.
|
||||
|
||||
This binding can also optionally provide support to the hardware autoidle
|
||||
feature, see [1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/ti/autoidle.txt
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,divider-clock
|
||||
- ti,composite-divider-clock
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ti,dividers:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
array of integers defining divisors
|
||||
|
||||
ti,bit-shift:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
number of bits to shift the divider value
|
||||
maximum: 31
|
||||
default: 0
|
||||
|
||||
ti,min-div:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
min divisor for dividing the input clock rate, only
|
||||
needed if the first divisor is offset from the default value (1)
|
||||
minimum: 1
|
||||
default: 1
|
||||
|
||||
|
||||
ti,max-div:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
max divisor for dividing the input clock rate, only needed
|
||||
if ti,dividers is not defined.
|
||||
|
||||
ti,index-starts-at-one:
|
||||
type: boolean
|
||||
description:
|
||||
valid divisor programming starts at 1, not zero,
|
||||
only valid if ti,dividers is not defined
|
||||
|
||||
ti,index-power-of-two:
|
||||
type: boolean
|
||||
description:
|
||||
valid divisor programming must be a power of two,
|
||||
only valid if ti,dividers is not defined.
|
||||
|
||||
ti,autoidle-shift:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
bit shift of the autoidle enable bit for the clock,
|
||||
see [1].
|
||||
maximum: 31
|
||||
default: 0
|
||||
|
||||
ti,invert-autoidle-bit:
|
||||
type: boolean
|
||||
description:
|
||||
autoidle is enabled by setting the bit to 0,
|
||||
see [1]
|
||||
|
||||
ti,set-rate-parent:
|
||||
type: boolean
|
||||
description:
|
||||
clk_set_rate is propagated to parent |
|
||||
|
||||
ti,latch-bit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
latch the divider value to HW, only needed if the register
|
||||
compatible access requires this. As an example dra76x DPLL_GMAC
|
||||
H14 divider implements such behavior.
|
||||
|
||||
dependentSchemas:
|
||||
ti,dividers:
|
||||
properties:
|
||||
ti,min-div: false
|
||||
ti,max-div: false
|
||||
ti,index-power-of-two: false
|
||||
ti,index-starts-at-one: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-controller@190 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_usb_ck>;
|
||||
ti,max-div = <127>;
|
||||
reg = <0x190>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
clock-controller@528 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&abe_clk>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x528>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
|
||||
clock-controller@a40 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0a40>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
};
|
||||
71
dts/upstream/Bindings/clock/ti/ti,interface-clock.yaml
Normal file
71
dts/upstream/Bindings/clock/ti/ti,interface-clock.yaml
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti/ti,interface-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments interface clock.
|
||||
|
||||
maintainers:
|
||||
- Tero Kristo <kristo@kernel.org>
|
||||
|
||||
description: |
|
||||
This clock is quite much similar to the basic gate-clock[1], however,
|
||||
it supports a number of additional features, including
|
||||
companion clock finding (match corresponding functional gate
|
||||
clock) and hardware autoidle enable / disable.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,omap3-interface-clock # basic OMAP3 interface clock
|
||||
- ti,omap3-no-wait-interface-clock # interface clock which has no hardware
|
||||
# capability for waiting clock to be ready
|
||||
- ti,omap3-hsotgusb-interface-clock # interface clock with USB specific HW handling
|
||||
- ti,omap3-dss-interface-clock # interface clock with DSS specific HW handling
|
||||
- ti,omap3-ssi-interface-clock # interface clock with SSI specific HW handling
|
||||
- ti,am35xx-interface-clock # interface clock with AM35xx specific HW handling
|
||||
- ti,omap2430-interface-clock # interface clock with OMAP2430 specific HW handling
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ti,bit-shift:
|
||||
description:
|
||||
bit shift for the bit enabling/disabling the clock
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
maximum: 31
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
aes1_ick: clock-controller@3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
125
dts/upstream/Bindings/clock/ti/ti,mux-clock.yaml
Normal file
125
dts/upstream/Bindings/clock/ti/ti,mux-clock.yaml
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments mux clock
|
||||
|
||||
maintainers:
|
||||
- Tero Kristo <kristo@kernel.org>
|
||||
|
||||
description: |
|
||||
This clock assumes a register-mapped multiplexer with multiple inpt clock
|
||||
signals or parents, one of which can be selected as output. This clock does
|
||||
not gate or adjust the parent rate via a divider or multiplier.
|
||||
|
||||
By default the "clocks" property lists the parents in the same order
|
||||
as they are programmed into the register. E.g:
|
||||
|
||||
clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
|
||||
|
||||
Results in programming the register as follows:
|
||||
|
||||
register value selected parent clock
|
||||
0 foo_clock
|
||||
1 bar_clock
|
||||
2 baz_clock
|
||||
|
||||
Some clock controller IPs do not allow a value of zero to be programmed
|
||||
into the register, instead indexing begins at 1. The optional property
|
||||
"index-starts-at-one" modified the scheme as follows:
|
||||
|
||||
register value selected clock parent
|
||||
1 foo_clock
|
||||
2 bar_clock
|
||||
3 baz_clock
|
||||
|
||||
The binding must provide the register to control the mux. Optionally
|
||||
the number of bits to shift the control field in the register can be
|
||||
supplied. If the shift value is missing it is the same as supplying
|
||||
a zero shift.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,mux-clock
|
||||
- ti,composite-mux-clock
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clocks: true
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ti,bit-shift:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Number of bits to shift the bit-mask
|
||||
maximum: 31
|
||||
default: 0
|
||||
|
||||
ti,index-starts-at-one:
|
||||
type: boolean
|
||||
description:
|
||||
Valid input select programming starts at 1, not zero
|
||||
|
||||
ti,set-rate-parent:
|
||||
type: boolean
|
||||
description:
|
||||
clk_set_rate is propagated to parent clock,
|
||||
not supported by the composite-mux-clock subtype.
|
||||
|
||||
ti,latch-bit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Latch the mux value to HW, only needed if the register
|
||||
access requires this. As an example, dra7x DPLL_GMAC H14 muxing
|
||||
implements such behavior.
|
||||
maximum: 31
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,composite-mux-clock
|
||||
then:
|
||||
properties:
|
||||
ti,set-rate-parent: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-controller@110 {
|
||||
compatible = "ti,mux-clock";
|
||||
reg = <0x0110>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>;
|
||||
ti,index-starts-at-one;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
clock-controller@120 {
|
||||
compatible = "ti,composite-mux-clock";
|
||||
reg = <0x0120>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&core_96m_fck>, <&mcbsp_clks>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
};
|
||||
|
|
@ -39,6 +39,11 @@ properties:
|
|||
- const: clk_in1
|
||||
- const: s_axi_aclk
|
||||
|
||||
xlnx,static-config:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Indicate whether the core has been configured without support for dynamic
|
||||
runtime reconfguration of the clocking primitive MMCM/PLL.
|
||||
|
||||
xlnx,speed-grade:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
|
@ -70,6 +75,7 @@ examples:
|
|||
compatible = "xlnx,clocking-wizard";
|
||||
reg = <0xb0000000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
xlnx,static-config;
|
||||
xlnx,speed-grade = <1>;
|
||||
xlnx,nr-outputs = <6>;
|
||||
clock-names = "clk_in1", "s_axi_aclk";
|
||||
|
|
|
|||
|
|
@ -253,6 +253,46 @@ properties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
sink-wait-cap-time-ms:
|
||||
description: Represents the max time in ms that USB Type-C port (in sink
|
||||
role) should wait for the port partner (source role) to send source caps.
|
||||
SinkWaitCap timer starts when port in sink role attaches to the source.
|
||||
This timer will stop when sink receives PD source cap advertisement before
|
||||
timeout in which case it'll move to capability negotiation stage. A
|
||||
timeout leads to a hard reset message by the port.
|
||||
minimum: 310
|
||||
maximum: 620
|
||||
default: 310
|
||||
|
||||
ps-source-off-time-ms:
|
||||
description: Represents the max time in ms that a DRP in source role should
|
||||
take to turn off power after the PsSourceOff timer starts. PsSourceOff
|
||||
timer starts when a sink's PHY layer receives EOP of the GoodCRC message
|
||||
(corresponding to an Accept message sent in response to a PR_Swap or a
|
||||
FR_Swap request). This timer stops when last bit of GoodCRC EOP
|
||||
corresponding to the received PS_RDY message is transmitted by the PHY
|
||||
layer. A timeout shall lead to error recovery in the type-c port.
|
||||
minimum: 750
|
||||
maximum: 920
|
||||
default: 920
|
||||
|
||||
cc-debounce-time-ms:
|
||||
description: Represents the max time in ms that a port shall wait to
|
||||
determine if it's attached to a partner.
|
||||
minimum: 100
|
||||
maximum: 200
|
||||
default: 200
|
||||
|
||||
sink-bc12-completion-time-ms:
|
||||
description: Represents the max time in ms that a port in sink role takes
|
||||
to complete Battery Charger (BC1.2) Detection. BC1.2 detection is a
|
||||
hardware mechanism, which in some TCPC implementations, can run in
|
||||
parallel once the Type-C connection state machine reaches the "potential
|
||||
connect as sink" state. In TCPCs where this causes delays to respond to
|
||||
the incoming PD messages, sink-bc12-completion-time-ms is used to delay
|
||||
PD negotiation till BC1.2 detection completes.
|
||||
default: 0
|
||||
|
||||
dependencies:
|
||||
sink-vdos-v1: [ sink-vdos ]
|
||||
sink-vdos: [ sink-vdos-v1 ]
|
||||
|
|
@ -380,7 +420,7 @@ examples:
|
|||
};
|
||||
|
||||
# USB-C connector attached to a typec port controller(ptn5110), which has
|
||||
# power delivery support and enables drp.
|
||||
# power delivery support, explicitly defines time properties and enables drp.
|
||||
- |
|
||||
#include <dt-bindings/usb/pd.h>
|
||||
typec: ptn5110 {
|
||||
|
|
@ -393,6 +433,10 @@ examples:
|
|||
sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
|
||||
PDO_VAR(5000, 12000, 2000)>;
|
||||
op-sink-microwatt = <10000000>;
|
||||
sink-wait-cap-time-ms = <465>;
|
||||
ps-source-off-time-ms = <835>;
|
||||
cc-debounce-time-ms = <101>;
|
||||
sink-bc12-completion-time-ms = <500>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ properties:
|
|||
- enum:
|
||||
- qcom,qcm2290-cpufreq-hw
|
||||
- qcom,sc7180-cpufreq-hw
|
||||
- qcom,sc8180x-cpufreq-hw
|
||||
- qcom,sdm670-cpufreq-hw
|
||||
- qcom,sdm845-cpufreq-hw
|
||||
- qcom,sm6115-cpufreq-hw
|
||||
|
|
@ -34,7 +35,9 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- qcom,qdu1000-cpufreq-epss
|
||||
- qcom,sa8255p-cpufreq-epss
|
||||
- qcom,sa8775p-cpufreq-epss
|
||||
- qcom,sar2130p-cpufreq-epss
|
||||
- qcom,sc7280-cpufreq-epss
|
||||
- qcom,sc8280xp-cpufreq-epss
|
||||
- qcom,sdx75-cpufreq-epss
|
||||
|
|
@ -107,6 +110,7 @@ allOf:
|
|||
contains:
|
||||
enum:
|
||||
- qcom,qcm2290-cpufreq-hw
|
||||
- qcom,sar2130p-cpufreq-epss
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
|
|
@ -130,7 +134,9 @@ allOf:
|
|||
contains:
|
||||
enum:
|
||||
- qcom,qdu1000-cpufreq-epss
|
||||
- qcom,sa8255p-cpufreq-epss
|
||||
- qcom,sc7180-cpufreq-hw
|
||||
- qcom,sc8180x-cpufreq-hw
|
||||
- qcom,sc8280xp-cpufreq-epss
|
||||
- qcom,sdm670-cpufreq-hw
|
||||
- qcom,sdm845-cpufreq-hw
|
||||
|
|
|
|||
48
dts/upstream/Bindings/cpufreq/qemu,virtual-cpufreq.yaml
Normal file
48
dts/upstream/Bindings/cpufreq/qemu,virtual-cpufreq.yaml
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpufreq/qemu,virtual-cpufreq.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Virtual CPUFreq
|
||||
|
||||
maintainers:
|
||||
- David Dai <davidai@google.com>
|
||||
- Saravana Kannan <saravanak@google.com>
|
||||
|
||||
description:
|
||||
Virtual CPUFreq is a virtualized driver in guest kernels that sends performance
|
||||
selection of its vCPUs as a hint to the host through MMIO regions. Each vCPU
|
||||
is associated with a performance domain which can be shared with other vCPUs.
|
||||
Each performance domain has its own set of registers for performance controls.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qemu,virtual-cpufreq
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description:
|
||||
Address and size of region containing performance controls for each of the
|
||||
performance domains. Regions for each performance domain is placed
|
||||
contiguously and contain registers for controlling DVFS(Dynamic Frequency
|
||||
and Voltage) characteristics. The size of the region is proportional to
|
||||
total number of performance domains.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpufreq@1040000 {
|
||||
compatible = "qemu,virtual-cpufreq";
|
||||
reg = <0x1040000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -114,8 +114,9 @@ patternProperties:
|
|||
table that specifies the PPID to LIODN mapping. Needed if the PAMU is
|
||||
used. Value is a 12 bit value where value is a LIODN ID for this JR.
|
||||
This property is normally set by boot firmware.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 0xfff
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- maximum: 0xfff
|
||||
|
||||
'^rtic@[0-9a-f]+$':
|
||||
type: object
|
||||
|
|
@ -186,8 +187,9 @@ patternProperties:
|
|||
Needed if the PAMU is used. Value is a 12 bit value where value
|
||||
is a LIODN ID for this JR. This property is normally set by boot
|
||||
firmware.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 0xfff
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- maximum: 0xfff
|
||||
|
||||
fsl,rtic-region:
|
||||
description:
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ properties:
|
|||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sa8775p-qce
|
||||
- qcom,sc7280-qce
|
||||
- qcom,sm6350-qce
|
||||
- qcom,sm8250-qce
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ properties:
|
|||
adi,dsi-lanes:
|
||||
description: Number of DSI data lanes connected to the DSI host.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 1, 2, 3, 4 ]
|
||||
enum: [ 2, 3, 4 ]
|
||||
|
||||
"#sound-dai-cells":
|
||||
const: 0
|
||||
|
|
|
|||
250
dts/upstream/Bindings/display/bridge/ite,it6263.yaml
Normal file
250
dts/upstream/Bindings/display/bridge/ite,it6263.yaml
Normal file
|
|
@ -0,0 +1,250 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ITE IT6263 LVDS to HDMI converter
|
||||
|
||||
maintainers:
|
||||
- Liu Ying <victor.liu@nxp.com>
|
||||
|
||||
description: |
|
||||
The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
|
||||
to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
|
||||
the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
|
||||
The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
|
||||
and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
|
||||
1.2 and backward compatible with DVI 1.0 specification.
|
||||
|
||||
The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
|
||||
with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
|
||||
an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
|
||||
|
||||
The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
|
||||
provided by the IT6263 in two interfaces: the four I2S input ports or the
|
||||
S/PDIF input port. With both interfaces the highest possible HBR frame rate
|
||||
is supported at up to 768KHz.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/display/lvds-dual-ports.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ite,it6263
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: audio master clock
|
||||
|
||||
clock-names:
|
||||
const: mclk
|
||||
|
||||
data-mapping:
|
||||
enum:
|
||||
- jeida-18
|
||||
- jeida-24
|
||||
- jeida-30
|
||||
- vesa-24
|
||||
- vesa-30
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
ivdd-supply:
|
||||
description: 1.8V digital logic power
|
||||
|
||||
ovdd-supply:
|
||||
description: 3.3V I/O pin power
|
||||
|
||||
txavcc18-supply:
|
||||
description: 1.8V HDMI analog frontend power
|
||||
|
||||
txavcc33-supply:
|
||||
description: 3.3V HDMI analog frontend power
|
||||
|
||||
pvcc1-supply:
|
||||
description: 1.8V HDMI frontend core PLL power
|
||||
|
||||
pvcc2-supply:
|
||||
description: 1.8V HDMI frontend filter PLL power
|
||||
|
||||
avcc-supply:
|
||||
description: 3.3V LVDS frontend power
|
||||
|
||||
anvdd-supply:
|
||||
description: 1.8V LVDS frontend analog power
|
||||
|
||||
apvdd-supply:
|
||||
description: 1.8V LVDS frontend PLL power
|
||||
|
||||
"#sound-dai-cells":
|
||||
const: 0
|
||||
|
||||
ite,i2s-audio-fifo-sources:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
enum: [0, 1, 2, 3]
|
||||
description:
|
||||
Each array element indicates the pin number of an I2S serial data input
|
||||
line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.
|
||||
|
||||
ite,rl-channel-swap-audio-sources:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
uniqueItems: true
|
||||
items:
|
||||
enum: [0, 1, 2, 3]
|
||||
description:
|
||||
Each array element indicates an audio source whose right channel and left
|
||||
channel are swapped by this converter. For I2S, the element is the pin
|
||||
number of an I2S serial data input line. For S/PDIF, the element is always
|
||||
0.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0: true
|
||||
|
||||
port@1:
|
||||
oneOf:
|
||||
- required: [dual-lvds-odd-pixels]
|
||||
- required: [dual-lvds-even-pixels]
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: video port for the HDMI output
|
||||
|
||||
port@3:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: sound input port
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- data-mapping
|
||||
- ivdd-supply
|
||||
- ovdd-supply
|
||||
- txavcc18-supply
|
||||
- txavcc33-supply
|
||||
- pvcc1-supply
|
||||
- pvcc2-supply
|
||||
- avcc-supply
|
||||
- anvdd-supply
|
||||
- apvdd-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
/* single-link LVDS input */
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hdmi@4c {
|
||||
compatible = "ite,it6263";
|
||||
reg = <0x4c>;
|
||||
data-mapping = "jeida-24";
|
||||
reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
|
||||
ivdd-supply = <®_buck5>;
|
||||
ovdd-supply = <®_vext_3v3>;
|
||||
txavcc18-supply = <®_buck5>;
|
||||
txavcc33-supply = <®_vext_3v3>;
|
||||
pvcc1-supply = <®_buck5>;
|
||||
pvcc2-supply = <®_buck5>;
|
||||
avcc-supply = <®_vext_3v3>;
|
||||
anvdd-supply = <®_buck5>;
|
||||
apvdd-supply = <®_buck5>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
it6263_lvds_link1: endpoint {
|
||||
remote-endpoint = <&ldb_lvds_ch0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
it6263_out: endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
/* dual-link LVDS input */
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hdmi@4c {
|
||||
compatible = "ite,it6263";
|
||||
reg = <0x4c>;
|
||||
data-mapping = "jeida-24";
|
||||
reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
|
||||
ivdd-supply = <®_buck5>;
|
||||
ovdd-supply = <®_vext_3v3>;
|
||||
txavcc18-supply = <®_buck5>;
|
||||
txavcc33-supply = <®_vext_3v3>;
|
||||
pvcc1-supply = <®_buck5>;
|
||||
pvcc2-supply = <®_buck5>;
|
||||
avcc-supply = <®_vext_3v3>;
|
||||
anvdd-supply = <®_buck5>;
|
||||
apvdd-supply = <®_buck5>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dual-lvds-odd-pixels;
|
||||
|
||||
it6263_lvds_link1_dual: endpoint {
|
||||
remote-endpoint = <&ldb_lvds_ch0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dual-lvds-even-pixels;
|
||||
|
||||
it6263_lvds_link2_dual: endpoint {
|
||||
remote-endpoint = <&ldb_lvds_ch1>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
it6263_out_dual: endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -81,9 +81,22 @@ properties:
|
|||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
unevaluatedProperties: false
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
description: Parallel RGB input port
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/graph.yaml#/$defs/endpoint-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
bus-width:
|
||||
description:
|
||||
Endpoint bus width.
|
||||
enum: [ 16, 18, 24 ]
|
||||
default: 24
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: HDMI output port
|
||||
|
|
|
|||
57
dts/upstream/Bindings/display/bridge/ti,tdp158.yaml
Normal file
57
dts/upstream/Bindings/display/bridge/ti,tdp158.yaml
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/ti,tdp158.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI TDP158 HDMI to TMDS Redriver
|
||||
|
||||
maintainers:
|
||||
- Arnaud Vrac <avrac@freebox.fr>
|
||||
- Pierre-Hugues Husson <phhusson@freebox.fr>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,tdp158
|
||||
|
||||
# The reg property is required if and only if the device is connected
|
||||
# to an I2C bus. In pin strap mode, reg must not be specified.
|
||||
reg:
|
||||
description: I2C address of the device
|
||||
|
||||
# Pin 36 = Operation Enable / Reset Pin
|
||||
# OE = L: Power Down Mode
|
||||
# OE = H: Normal Operation
|
||||
# Internal weak pullup - device resets on H to L transitions
|
||||
enable-gpios:
|
||||
description: GPIO controlling bridge enable
|
||||
|
||||
vcc-supply:
|
||||
description: Power supply 3.3V
|
||||
|
||||
vdd-supply:
|
||||
description: Power supply 1.1V
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Bridge input
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Bridge output
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- vcc-supply
|
||||
- vdd-supply
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -60,6 +60,10 @@ properties:
|
|||
data-lines:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 16, 18, 24 ]
|
||||
deprecated: true
|
||||
|
||||
bus-width:
|
||||
enum: [ 16, 18, 24 ]
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
|
|
|||
|
|
@ -119,7 +119,6 @@ Optional properties:
|
|||
- interface-pix-fmt: How this display is connected to the
|
||||
display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
|
||||
and "lvds666".
|
||||
- edid: verbatim EDID data block describing attached display.
|
||||
- ddc: phandle describing the i2c bus handling the display data
|
||||
channel
|
||||
- port@[0-1]: Port nodes with endpoint definitions as defined in
|
||||
|
|
@ -131,7 +130,6 @@ example:
|
|||
|
||||
disp0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
edid = [edid-data];
|
||||
interface-pix-fmt = "rgb24";
|
||||
|
||||
port@0 {
|
||||
|
|
|
|||
|
|
@ -62,7 +62,6 @@ Required properties:
|
|||
display-timings are used instead.
|
||||
|
||||
Optional properties (required if display-timings are used):
|
||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
||||
- display-timings : A node that describes the display timings as defined in
|
||||
Documentation/devicetree/bindings/display/panel/display-timing.txt.
|
||||
- fsl,data-mapping : should be "spwg" or "jeida"
|
||||
|
|
|
|||
|
|
@ -26,12 +26,17 @@ description: |
|
|||
Device compatible with those specifications have been marketed under the
|
||||
FPD-Link and FlatLink brands.
|
||||
|
||||
This bindings also supports 30-bit data mapping compatible with JEIDA and
|
||||
VESA.
|
||||
|
||||
properties:
|
||||
data-mapping:
|
||||
enum:
|
||||
- jeida-18
|
||||
- jeida-24
|
||||
- jeida-30
|
||||
- vesa-24
|
||||
- vesa-30
|
||||
description: |
|
||||
The color signals mapping order.
|
||||
|
||||
|
|
@ -60,6 +65,19 @@ properties:
|
|||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
|
||||
DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
|
||||
|
||||
- "jeida-30" - 30-bit data mapping compatible with JEIDA and VESA. Data
|
||||
are transferred as follows on 5 LVDS lanes.
|
||||
|
||||
Slot 0 1 2 3 4 5 6
|
||||
________________ _________________
|
||||
Clock \_______________________/
|
||||
______ ______ ______ ______ ______ ______ ______
|
||||
DATA0 ><__G4__><__R9__><__R8__><__R7__><__R6__><__R5__><__R4__><
|
||||
DATA1 ><__B5__><__B4__><__G9__><__G8__><__G7__><__G6__><__G5__><
|
||||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B9__><__B8__><__B7__><__B6__><
|
||||
DATA3 ><_CTL3_><__B3__><__B2__><__G3__><__G2__><__R3__><__R2__><
|
||||
DATA4 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
|
||||
|
||||
- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
|
||||
Data are transferred as follows on 4 LVDS lanes.
|
||||
|
||||
|
|
@ -72,6 +90,19 @@ properties:
|
|||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
|
||||
DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
|
||||
|
||||
- "vesa-30" - 30-bit data mapping compatible with VESA. Data are
|
||||
transferred as follows on 5 LVDS lanes.
|
||||
|
||||
Slot 0 1 2 3 4 5 6
|
||||
________________ _________________
|
||||
Clock \_______________________/
|
||||
______ ______ ______ ______ ______ ______ ______
|
||||
DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
|
||||
DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
|
||||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
|
||||
DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
|
||||
DATA4 ><_CTL3_><__B9__><__B8__><__G9__><__G8__><__R9__><__R8__><
|
||||
|
||||
Control signals are mapped as follows.
|
||||
|
||||
CTL0: HSync
|
||||
|
|
|
|||
63
dts/upstream/Bindings/display/lvds-dual-ports.yaml
Normal file
63
dts/upstream/Bindings/display/lvds-dual-ports.yaml
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/lvds-dual-ports.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Dual-link LVDS Display Common Properties
|
||||
|
||||
maintainers:
|
||||
- Liu Ying <victor.liu@nxp.com>
|
||||
|
||||
description: |
|
||||
Common properties for LVDS displays with dual LVDS links. Extend LVDS display
|
||||
common properties defined in lvds.yaml.
|
||||
|
||||
Dual-link LVDS displays receive odd pixels and even pixels separately from
|
||||
the dual LVDS links. One link receives odd pixels and the other receives
|
||||
even pixels. Some of those displays may also use only one LVDS link to
|
||||
receive all pixels, being odd and even agnostic.
|
||||
|
||||
allOf:
|
||||
- $ref: lvds.yaml#
|
||||
|
||||
properties:
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
patternProperties:
|
||||
'^port@[01]$':
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: |
|
||||
port@0 represents the first LVDS input link.
|
||||
port@1 represents the second LVDS input link.
|
||||
|
||||
properties:
|
||||
dual-lvds-odd-pixels:
|
||||
type: boolean
|
||||
description: LVDS input link for odd pixels
|
||||
|
||||
dual-lvds-even-pixels:
|
||||
type: boolean
|
||||
description: LVDS input link for even pixels
|
||||
|
||||
oneOf:
|
||||
- required: [dual-lvds-odd-pixels]
|
||||
- required: [dual-lvds-even-pixels]
|
||||
- properties:
|
||||
dual-lvds-odd-pixels: false
|
||||
dual-lvds-even-pixels: false
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- port@0
|
||||
- required:
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- ports
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
|
@ -62,6 +62,27 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: AAL input port
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
AAL output to the next component's input, for example could be one
|
||||
of many gamma, overdrive or other blocks.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -89,5 +110,24 @@ examples:
|
|||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
aal0_in: endpoint {
|
||||
remote-endpoint = <&ccorr0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
aal0_out: endpoint {
|
||||
remote-endpoint = <&gamma0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -57,6 +57,27 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: CCORR input port
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
CCORR output to the input of the next desired component in the
|
||||
display pipeline, usually only one of the available AAL blocks.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -65,6 +65,28 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: COLOR input port
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
COLOR output to the input of the next desired component in the
|
||||
display pipeline, for example one of the available CCORR or AAL
|
||||
blocks.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -56,6 +56,28 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DITHER input, usually from a POSTMASK or GAMMA block.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
DITHER output to the input of the next desired component in the
|
||||
display pipeline, for example one of the available DSC compressors,
|
||||
DP_INTF, DSI, LVDS or others.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -42,6 +42,9 @@ properties:
|
|||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#sound-dai-cells':
|
||||
const: 0
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
properties:
|
||||
|
|
@ -85,7 +88,21 @@ required:
|
|||
- ports
|
||||
- max-linkrate-mhz
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: /schemas/sound/dai-common.yaml#
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- mediatek,mt8188-dp-tx
|
||||
- mediatek,mt8195-dp-tx
|
||||
then:
|
||||
properties:
|
||||
'#sound-dai-cells': false
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -81,13 +81,34 @@ properties:
|
|||
Output port node. This port should be connected to the input port of an
|
||||
attached HDMI, LVDS or DisplayPort encoder chip.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPI input port
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPI output to an HDMI, LVDS or DisplayPort encoder input
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- port
|
||||
|
||||
oneOf:
|
||||
- required:
|
||||
- port
|
||||
- required:
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
@ -96,7 +117,7 @@ examples:
|
|||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
|
||||
dpi0: dpi@1401d000 {
|
||||
dpi: dpi@1401d000 {
|
||||
compatible = "mediatek,mt8173-dpi";
|
||||
reg = <0x1401d000 0x1000>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
|
|
|||
|
|
@ -49,6 +49,30 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Display Stream Compression input, usually from one of the DITHER
|
||||
or MERGE blocks.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Display Stream Compression output to the input of the next desired
|
||||
component in the display pipeline, for example to MERGE, DP_INTF,
|
||||
DPI or DSI.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -77,6 +77,26 @@ properties:
|
|||
Output port node. This port should be connected to the input
|
||||
port of an attached DSI panel or DSI-to-eDP encoder chip.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input ports can have multiple endpoints, each of those connects
|
||||
to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DSI input port, usually from DITHER, DSC or MERGE
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
DSI output to an attached DSI panel, or a DSI-to-X encoder chip
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -86,7 +106,12 @@ required:
|
|||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- port
|
||||
|
||||
oneOf:
|
||||
- required:
|
||||
- port
|
||||
- required:
|
||||
- ports
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -110,6 +110,28 @@ properties:
|
|||
include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
|
||||
function block.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: ETHDR input, usually from one of the MERGE blocks.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
ETHDR output to the input of the next desired component in the
|
||||
display pipeline, for example one of the available MERGE blocks,
|
||||
or others.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -65,6 +65,25 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: GAMMA input, usually from one of the AAL blocks.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
GAMMA output to the input of the next desired component in the
|
||||
display pipeline, for example one of the available DITHER or
|
||||
POSTMASK blocks.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -77,6 +77,29 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
MERGE input port, usually from DITHER, DPI, DSC, DSI, MDP_RDMA,
|
||||
ETHDR or even from a different MERGE block
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
MERGE output to a DSC, DPI, DP_INTF, DSI, ETHDR, Write DMA, or
|
||||
a different MERGE block, or others.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
resets:
|
||||
description: reset controller
|
||||
See Documentation/devicetree/bindings/reset/reset.txt for details.
|
||||
|
|
|
|||
|
|
@ -38,6 +38,28 @@ properties:
|
|||
items:
|
||||
- description: OD Clock
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: OD input port, usually from an AAL block
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
OD output to the input of the next desired component in the
|
||||
display pipeline, for example one of the available RDMA or
|
||||
other blocks.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -57,6 +57,28 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: OVL input port from MMSYS, VDOSYS or other OVLs
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
OVL output to the input of the next desired component in the
|
||||
display pipeline, for example one of the available COLOR, RDMA
|
||||
or WDMA blocks.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -75,6 +75,28 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: OVL input port from MMSYS or one of multiple VDOSYS
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
OVL output to the input of the next desired component in the
|
||||
display pipeline, for example one of the available COLOR, RDMA
|
||||
or WDMA blocks.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -52,6 +52,27 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: POSTMASK input port, usually from GAMMA
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
POSTMASK output to the input of the next desired component in the
|
||||
display pipeline, for example one of the available DITHER blocks.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -87,6 +87,28 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: RDMA input port, usually from MMSYS, OD or OVL
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
RDMA output to the input of the next desired component in the
|
||||
display pipeline, for example one of the available COLOR, DPI,
|
||||
DSI, MERGE or UFOE blocks.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -43,6 +43,27 @@ properties:
|
|||
items:
|
||||
- description: UFOe Clock
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description:
|
||||
Input and output ports can have multiple endpoints, each of those
|
||||
connects to either the primary, secondary, etc, display pipeline.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: UFOE input, usually from one of the RDMA blocks.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
UFOE output to the input of the next desired component in the
|
||||
display pipeline, usually one of the available DSI blocks.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ properties:
|
|||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,sa8775p-dp
|
||||
- qcom,sc7180-dp
|
||||
- qcom,sc7280-dp
|
||||
- qcom,sc7280-edp
|
||||
|
|
|
|||
|
|
@ -125,6 +125,7 @@ allOf:
|
|||
enum:
|
||||
- qcom,adreno-gmu-635.0
|
||||
- qcom,adreno-gmu-660.1
|
||||
- qcom,adreno-gmu-663.0
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
|
|
|
|||
241
dts/upstream/Bindings/display/msm/qcom,sa8775p-mdss.yaml
Normal file
241
dts/upstream/Bindings/display/msm/qcom,sa8775p-mdss.yaml
Normal file
|
|
@ -0,0 +1,241 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SA87755P Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Mahadevan <quic_mahap@quicinc.com>
|
||||
|
||||
description:
|
||||
SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
|
||||
DPU display controller, DP interfaces and EDP etc.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sa8775p-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB
|
||||
- description: Display hf AXI
|
||||
- description: Display core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
maxItems: 3
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 3
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sa8775p-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sa8775p-dp
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
compatible = "qcom,sa8775p-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
|
||||
<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
|
||||
interconnect-names = "mdp0-mem",
|
||||
"mdp1-mem",
|
||||
"cpu-cfg";
|
||||
|
||||
|
||||
resets = <&dispcc_core_bcr>;
|
||||
power-domains = <&dispcc_gdsc>;
|
||||
|
||||
clocks = <&dispcc_ahb_clk>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc_mdp_clk>;
|
||||
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x1000 0x402>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sa8775p-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc_ahb_clk>,
|
||||
<&dispcc_mdp_lut_clk>,
|
||||
<&dispcc_mdp_clk>,
|
||||
<&dispcc_mdp_vsync_clk>;
|
||||
clock-names = "nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&dispcc_mdp_vsync_clk>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdss0_mdp_opp_table>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss0>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf0_out: endpoint {
|
||||
remote-endpoint = <&mdss0_dp0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss0_mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-375000000 {
|
||||
opp-hz = /bits/ 64 <375000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
|
||||
opp-575000000 {
|
||||
opp-hz = /bits/ 64 <575000000>;
|
||||
required-opps = <&rpmhpd_opp_turbo>;
|
||||
};
|
||||
|
||||
opp-650000000 {
|
||||
opp-hz = /bits/ 64 <650000000>;
|
||||
required-opps = <&rpmhpd_opp_turbo_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
displayport-controller@af54000 {
|
||||
compatible = "qcom,sa8775p-dp";
|
||||
|
||||
pinctrl-0 = <&dp_hot_plug_det>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
reg = <0xaf54000 0x104>,
|
||||
<0xaf54200 0x0c0>,
|
||||
<0xaf55000 0x770>,
|
||||
<0xaf56000 0x09c>;
|
||||
|
||||
interrupt-parent = <&mdss0>;
|
||||
interrupts = <12>;
|
||||
|
||||
clocks = <&dispcc_mdss_ahb_clk>,
|
||||
<&dispcc_dptx0_aux_clk>,
|
||||
<&dispcc_dptx0_link_clk>,
|
||||
<&dispcc_dptx0_link_intf_clk>,
|
||||
<&dispcc_dptx0_pixel0_clk>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
|
||||
<&dispcc_mdss_dptx0_pixel0_clk_src>;
|
||||
assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>;
|
||||
|
||||
phys = <&mdss0_edp_phy>;
|
||||
phy-names = "dp";
|
||||
|
||||
operating-points-v2 = <&dp_opp_table>;
|
||||
power-domains = <&rpmhpd SA8775P_MMCX>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdss0_dp0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdss0_dp_out: endpoint { };
|
||||
};
|
||||
};
|
||||
|
||||
dp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-270000000 {
|
||||
opp-hz = /bits/ 64 <270000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-540000000 {
|
||||
opp-hz = /bits/ 64 <540000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-810000000 {
|
||||
opp-hz = /bits/ 64 <810000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -7,13 +7,21 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Qualcomm Display DPU on SC7280
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-dpu
|
||||
enum:
|
||||
- qcom,sc7280-dpu
|
||||
- qcom,sc8280xp-dpu
|
||||
- qcom,sm8350-dpu
|
||||
- qcom,sm8450-dpu
|
||||
- qcom,sm8550-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -1,122 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SC8280XP Display Processing Unit
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for SC8280XP Display Processing Unit.
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc8280xp-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display hf axi clock
|
||||
- description: Display sf axi clock
|
||||
- description: Display ahb clock
|
||||
- description: Display lut clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: nrt_bus
|
||||
- const: iface
|
||||
- const: lut
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc8280xp-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <460000000>,
|
||||
<19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SC8280XP_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss0>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp1_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp3_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp2_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8150-dpu
|
||||
enum:
|
||||
- qcom,sm8150-dpu
|
||||
- qcom,sm8250-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -1,99 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8250 Display DPU
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8250-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display ahb clock
|
||||
- description: Display hf axi clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8250.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm8250-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
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Add table
Reference in a new issue