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85854bc332
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/ Tested-by: Heiko Stuebner <heiko@sntech.de> # rk3588-rock5b, rk3588-jaguar, # rk3588-tiger (pending patch)
51 lines
1.1 KiB
YAML
51 lines
1.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mobileye EyeQ5 clock controller
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description:
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The EyeQ5 clock controller handles 10 read-only PLLs derived from the main
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crystal clock. It also exposes one divider clock, a child of one of the PLLs.
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Its registers live in a shared region called OLB.
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maintainers:
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- Grégory Clement <gregory.clement@bootlin.com>
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- Théo Lebrun <theo.lebrun@bootlin.com>
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- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
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properties:
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compatible:
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const: mobileye,eyeq5-clk
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: plls
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- const: ospi
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"#clock-cells":
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const: 1
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clocks:
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maxItems: 1
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description:
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Input parent clock to all PLLs. Expected to be the main crystal.
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clock-names:
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items:
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- const: ref
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required:
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- compatible
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- reg
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- reg-names
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- "#clock-cells"
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- clocks
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- clock-names
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additionalProperties: false
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