u-boot/dts/upstream/Bindings/clock/microchip,lan966x-gck.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip LAN966X Generic Clock Controller

maintainers:
  - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>

description: |
  The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
  ddr_clk and sys_clk. This clock controller generates and supplies
  clock to various peripherals within the SoC.

properties:
  compatible:
    oneOf:
      - enum:
          - microchip,lan966x-gck
          - microchip,lan9691-gck
      - items:
          - enum:
              - microchip,lan9698-gck
              - microchip,lan9696-gck
              - microchip,lan9694-gck
              - microchip,lan9693-gck
              - microchip,lan9692-gck
          - const: microchip,lan9691-gck

  reg:
    minItems: 1
    items:
      - description: Generic clock registers
      - description: Optional gate clock registers

  clocks:
    items:
      - description: CPU clock source
      - description: DDR clock source
      - description: System clock source

  clock-names:
    items:
      - const: cpu
      - const: ddr
      - const: sys

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clks: clock-controller@e00c00a8 {
        compatible = "microchip,lan966x-gck";
        #clock-cells = <1>;
        clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
        clock-names = "cpu", "ddr", "sys";
        reg = <0xe00c00a8 0x38>;
    };
...