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d8a7100d65
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git [rockchip fixes from Jonas Karlman via IRC]
65 lines
1.5 KiB
YAML
65 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on sar2130p
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maintainers:
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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description: |
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Qualcomm global clock control module provides the clocks, resets and
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power domains on sar2130p.
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See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h
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properties:
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compatible:
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const: qcom,sar2130p-gcc
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clocks:
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items:
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- description: XO reference clock
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- description: Sleep clock
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- description: PCIe 0 pipe clock
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- description: PCIe 1 pipe clock
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- description: Primary USB3 PHY wrapper pipe clock
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protected-clocks:
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maxItems: 240
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power-domains:
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maxItems: 1
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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gcc: clock-controller@100000 {
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compatible = "qcom,sar2130p-gcc";
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reg = <0x100000 0x1f4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&pcie_0_pipe_clk>,
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<&pcie_1_pipe_clk>,
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<&usb_0_ssphy>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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