This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.
Change-Id: Ib8b3339f32031a3657f6c349763a20a99fd828e7
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.
Change-Id: Iffbd8770fd4ff2f2176062469d22961cbaa160b4
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.
Change-Id: Ice3eb939664ffc62c1f586b641e37481f10ffff6
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Add MCDI driver to manage CPU idle states and optimize power consumption.
Signed-off-by: Kai Liang <kai.liang@mediatek.com>
Change-Id: I3a2e163730dd997dd72f2ebc1375dea38d728cb7
And mcusys drivers to enhance CPU power state control.
Signed-off-by: Kai Liang <kai.liang@mediatek.com>
Change-Id: I7d84407cebc16a5ab23359781574e9d02e90c58b
Add Centralized Power Control (CPC) module to manage CPU power states.
Signed-off-by: Kai Liang <kai.liang@mediatek.com>
Change-Id: I212155143018141c89427032f6a7d21243e750b7
Add topology module to support CPU power state control.
Signed-off-by: Kai Liang <kai.liang@mediatek.com>
Change-Id: I0cc1e5a426762b1b29bff1e940e077643da02e5e
Add SPMI and PMIF driver for PMIC communication
Change-Id: Iad1d90381d6dad6b3e92fd9d6a3ce02fa11d15f1
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Ref: https://linaro.atlassian.net/browse/TFC-669
The initial LTS document was created as pdf and was maintained in a
shared folder location, to avoid pdf getting lost and trying to find
where it is we decided to have LTS details part of docs in TF-A.
This patch directly reflects the data from pdf attached to TFC-669.
Any improvements or amends to this will be done at later phases based
on LTS maintainers comments and agreements.
Change-Id: I1434c29f0236161d2a127596e2cc528bf4cc3e85
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
The commit a6485b2b3b ("refactor(delay-timer): add timer
callback functions") is breaking DCC console due to uninitialized
timer ops structure. Fix it by moving generic delay timer init
prior to console setup to make sure that time is setup before DCC
console setup.
Fixes: a6485b2b3b ("refactor(delay-timer): add timer callback
functions")
Change-Id: I67910332773741c0b08f02feb232efab6356db12
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
After the change to allow overriding platform specific defaults [1],
the PLAT macro is forced to DEFAULT_PLAT in plat_helpers.mk. But this
makefile is also called for tools. For example in fiptool makefile, as
PLAT is reset to default plat (fvp), we cannot use specific platforms
plat_fiptool.mk files. Put back the setting of PLAT macro in Makefile.
[1]: 1b2fb6adb5 feat(build): add ability to define platform specific
defaults
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iadf8bc7fc831a728a9688d0afdd163c8dda737e5
Move console_switch_state(CONSOLE_FLAG_RUNTIME) to sp_min_main() so
that this becomes the last call before bl32/sp_min exits. This also
ensures that console_flush() is called before switching console state
to runtime.
This patch mimics the behavior of console_switch_state() call in BL31
per this patch
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/26771/4.
Change-Id: I5b562d02706b19bb8b14154be97b6e9ef4e2fd3b
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
* changes:
perf(psci): pass my_core_pos around instead of calling it repeatedly
refactor(psci): move timestamp collection to psci_pwrdown_cpu
refactor(psci): factor common code out of the standby finisher
refactor(psci): don't use PSCI_INVALID_PWR_LVL to signal OFF state
docs(psci): drop outdated cache maintenance comment
This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.
Change-Id: Ibff3df16b4c591384467771bc7cb316f1773f1ea
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Update DDR address map of BL32, BL33 and transfer list to support
AMD Versal Gen 2 platform's new memory map.
Change-Id: I757b2f67270034c8a3140e4bb0ac4d7e88b5d055
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
The build macro no longer coverts variable names to uppercase.
We need to convert it to uppercase to pass it on.
Change-Id: If808fc77bce71d575e2d43ff83c4d9bcdcc52326
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
FEAT_MOPS, mandatory from Arm v8.8, is typically managed in EL2.
However, in configurations where NS_EL2 is not enabled,
EL3 must set the HCRX_EL2.MSCEn bit to 1 to enable the feature.
This patch ensures FEAT_MOPS is enabled by setting HCRX_EL2.MSCEn to 1.
Change-Id: Ic4960e0cc14a44279156b79ded50de475b3b21c5
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
* changes:
feat(s32g274a): split early clock initialization
feat(s32g274a): enable MMU for BL31 stage
feat(s32g274a): dynamically map GIC regions
feat(s32g274a): enable MMU for BL2 stage
feat(s32g274a): dynamically map siul2 and fip img
feat(s32g274a): map each image before its loading
feat(nxp-clk): dynamic map of the clock modules
feat(s32g274a): increase the number of MMU regions
feat(s32g274a): add console mapping
For a couple of releases now we have officially withdrawn support for
building TF-A on Windows using the native environment, relying instead
on POSIX emulation layers like MSYS2, Mingw64, Cygwin or WSL.
This change removes the remainder of the OS compatibility layer
entirely, and migrates the build system over to explicitly relying on a
POSIX environment.
Change-Id: I8fb60d998162422e958009afd17eab826e3bc39b
Signed-off-by: Chris Kay <chris.kay@arm.com>
Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.
Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Enable the MMU and add two entries to map the BL31 code and data
regions. Additional mappings will be added dynamically, enhancing
flexibility and modularity during the porting process.
Change-Id: I333c34c58274a115f62f54730bba5b71165e3e36
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Dynamically add entries for the GIC distributor and all its
redistributors for the cases when the platform is booted using enabled
MMU.
Change-Id: Ia810ec2329993057173e8fc25620a3df59b1e55d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Enable the MMU and add two entries to map the BL2 code and data regions.
Additional mappings will be added dynamically, enhancing flexibility and
modularity during the porting process.
Change-Id: I107abf944dfdce9dcff47b08272a5001484de8a9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Dynamically map the remaining regions part of the BL2 stages using
dynamic regions.
Change-Id: Ia81666920b941218ddaa7d3244dfa5212525c75d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The regions used by the stages loaded by BL2 must be mapped before they
can be used.
Change-Id: Ia70f8c5f35d7930e2b20f1a26be0ad2cdfea2b1a
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add all clock modules as entries in MMU using dynamic regions.
Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.
Change-Id: Ib0dd2d0dbc9b4a574367141a7c96d76dd08e2c7f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
On some platforms plat_my_core_pos is a nontrivial function that takes a
bit of time and the compiler really doesn't like to inline. In the PSCI
library, at least, we have no need to keep repeatedly calling it and we
can instead pass it around as an argument. This saves on a lot of
redundant calls, speeding the library up a bit.
Change-Id: I137f69bea80d7cac90d7a20ffe98e1ba8d77246f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
psci_pwrdown_cpu has two callers, both of which save timestamps meant to
measure how much time the cache maintenance operations take. Move the
timestamp collection inside to save on a bit of code duplication.
Change-Id: Ia2e7168faf7773d99b696cbdb6c98db7b58e31cf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
psci_suspend_to_standby_finisher and psci_cpu_suspend_finish do mostly
the same stuff, besides the system management associated with their
respective wakeup paths. So bring the wake from standby path in line
with the wake from reset path - caller acquires locks and manages
context. This way both behave in vaguely the same way. We can also bring
their names in line so it's more apparent how they are different.
This is in preparation for cores waking from sleep, coming in another
patch. No functional change is expected.
Change-Id: I0e569d12f65d231606080faa0149d22efddc386d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
The target_pwrlvl field in the psci cpu data struct only stores the
highest power domain that a CPU_SUSPEND call affected, and is used to
resume those same domains on warm reset. If the cpu is otherwise OFF
(never turned on or CPU_OFF), then this needs to be the highest power
level because we don't know the highest level that will be off.
So skip the invalidation and always keep the field to the maximum value.
During suspend the field will be lowered to the appropriate value and
then put back after wakeup.
Also, do that in the suspend to standby path as well as it will have
been written before the sleep and it might end up incorrect.
Change-Id: I614272ec387e1d83023c94700780a0f538a9a6b6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
The comment was written when cache maintenance had to be considered when
calling this function. But that argument was dropped a while back and
this comment no longer makes any sense.
Change-Id: Ib68293f23cc3edca3010164dfe8866956b8e1a63
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Patch fc7dca72ba656e5f147487b20f9f0fb6eb39e116 changed the owning
security states of the TRBE and SPE buffers to NS. The thinking was that
this would assist SMCCC feature availability to more easily determine
if the feature is enabled or disabled. However, that only changed bit 0
while the SMCCC feature only looks at bit 1 so this change is redundant.
It was also meant to tighten security but that was done by
73d98e3759 instead.
Annoyingly, FEAT_TRBE has TRBIDR_EL1 which reports that programming is
allowed when the current security state owns the buffer even when the
MDCR_EL3 setting disallows this in practice.
So revert the functional aspect of the patch as it causes linux panics
with ERRATA_A520_2938996. Keep the defines as they are used elsewhere.
Change-Id: I39463d585df89aee44d1996137616da85d678f41
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
* changes:
feat(el3_spmc): ffa error handling in direct msg
feat(ff-a): support FFA_MSG_SEND_DIRECT_REQ2/RESP2
feat(ff-a): add FFA_MEM_PERM_GET/SET_SMC64
feat(el3-spmc): support Hob list to boot S-EL0 SP
feat(synquacer): add support Hob creation
fix(fvp): exclude extend memory map TZC regions
feat(fvp): add StandaloneMm manifest in fvp
feat(spm): use xfer list with Hob list in SPM_MM
