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Merge "fix(cm): change back owning security state when a feature is disabled" into integration
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commit
9ac82c4979
2 changed files with 6 additions and 12 deletions
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@ -42,19 +42,14 @@ void spe_disable(cpu_context_t *ctx)
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.NSPB: set to 0x2. After, Non-Secure state owns
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* the Profiling Buffer and accesses to Statistical Profiling and Profiling
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* Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3.
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* Profiling is disabled in Secure and Realm states.
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*
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* MDCR_EL3.NSPBE: Don't care as it was cleared during spe_enable and setting
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* this to 1 does not make sense as NSPBE{1} and NSPB{0b0x} is RESERVED.
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* MDCR_EL3.{NSPB,NSPBE} = 0b00, 0b0
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* Disable access of profiling buffer control registers from lower ELs
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* in any security state. Secure state owns the buffer.
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*
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* MDCR_EL3.EnPMSN (ARM v8.7): Clear the bit to trap access of PMSNEVFR_EL1
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* from EL2/EL1 to EL3.
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*/
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mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT);
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mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL3);
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mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_NSPBE_BIT | MDCR_EnPMSN_BIT);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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@ -35,13 +35,12 @@ void trbe_disable(cpu_context_t *ctx)
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.{NSTBE,NSTB} = 0b0, 0b10
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* MDCR_EL3.{NSTBE,NSTB} = 0b0, 0b00
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* Disable access of trace buffer control registers from lower ELs in
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* any security state. Non-secure owns the buffer.
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* any security state. Secure state owns the buffer.
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*/
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mdcr_el3_val &= ~(MDCR_NSTB(MDCR_NSTB_EL1));
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mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
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mdcr_el3_val |= MDCR_NSTB(MDCR_NSTB_EL3);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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