Commit graph

14732 commits

Author SHA1 Message Date
Chris Kay
d9db846766 build(romlib): de-duplicate ROMLib wrapper sources
The `romlib_generator.py` script may generate duplicate wrapper sources,
which is undesirable when using them to generate Makefile rules as Make
will warn about duplicated targets.

This change sorts the wrapper sources returned from this script, which
has the effect of also de-duplicating them.

Change-Id: I109607ef94f77113a48cc0d6e07877efd1971dbc
Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-06-04 11:08:53 +00:00
Chris Kay
df52e2600d fix(build): fix incorrectly-escaped armlink preprocessor definitions
Preprocessor definitions that are passed to armlink are currently not
correctly escaped, resulting in the shell trying to parse the
parentheses contained in some of the preprocessor definitions:

```
  LD      build/tegra/t210/release/bl31/bl31.elf
/bin/sh: 1: Syntax error: "(" unexpected
```

This change ensures that these preprocessor definitions are adequately
escaped for the shell.

Change-Id: I9d2c60fa60c0aa00770417a68f900e9fb84b4669
Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-06-04 11:06:38 +00:00
Soby Mathew
20307efa5e Merge "docs(gpt): update GPT library documentation" into integration 2024-06-03 15:26:05 +02:00
AlexeiFedorov
c944952bc3 docs(gpt): update GPT library documentation
This patch updates GPT library design documentation
with the changes introduced by patches which add
support for large GPT mappings and configuration of
memory size protected by bitlock.

Change-Id: I1f97fa8f003deb07a5f32b7237c1927581a788c8
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
2024-06-03 12:13:06 +01:00
Manish V Badarkhe
a13449da37 Merge "feat(stm32mp15): remove OP-TEE shared mem" into integration 2024-06-03 09:50:20 +02:00
Manish V Badarkhe
6d5048f025 Merge "feat(tc): add default SLC policy for the gpu" into integration 2024-06-03 09:39:10 +02:00
Manish V Badarkhe
adf19215f9 Merge "feat(tc): support full-HD resolution for the FVP model" into integration 2024-06-03 09:39:01 +02:00
Lauren Wehrmeister
aff731af1c Merge "chore(errata-abi): minor variable rename" into integration 2024-05-30 18:58:11 +02:00
Govindraj Raja
5dd9068853 chore(errata-abi): minor variable rename
'cpu_partnumber' variable part of 'em_cpu_list' actually contains the
cpu midr value and not the actual part number. The part number is
extracted from midr value in 'non_arm_interconnect_errata' function.

So 'cpu_partnumber' is misleading and the actual value is midr, thus
rename it to 'cpu_midr'.

Change-Id: I4bfe71ce24542d508e2bcf39a1097724d14c4511
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-05-30 10:39:24 -05:00
Manish Pandey
95bf32e77c Merge changes from topic "us_mhuv3" into integration
* changes:
  feat(tc): add MHUv3 addresses between RSS and AP
  feat(tc): specify MHU version based on platform
  feat(tc): bind SCMI over MHUv3 for TC3
  feat(tc): add MHUv3 DT binding for TC3
  feat(tc): add MHUv3 doorbell support on TC3
  refactor(tc): change tc_scmi_plat_info to single structure
2024-05-30 17:10:22 +02:00
Angel Rodriguez Garcia
bebefe0f33 feat(tc): add default SLC policy for the gpu
As per the GPU integration guide, adding the PBHA INT overrides to
influence the GPU allocation policy for the System Level Cache (SLC).

This commit uses SLC policy #23, which is the Arm SLC cache policy
number for GPUs. The cache policy #23 may not be optimal for all
workloads, although it outperforms other policies on the tested data
sets.

Change-Id: I19ddbcf52a2f01af0ab6dfd7cc25b2e438b9014a
Signed-off-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
2024-05-30 14:23:19 +01:00
Manish Pandey
55c7efc494 Merge "refactor(cm): move mpam registers into el2 context" into integration 2024-05-30 13:48:04 +02:00
Joanna Farley
76e2698a08 Merge changes from topic "gr/cpu_ren" into integration
* changes:
  chore: rename Blackhawk to Cortex-X925
  chore: rename Chaberton to Cortex-A725
2024-05-30 08:52:15 +02:00
Govindraj Raja
bbe94cddc4 chore: rename Blackhawk to Cortex-X925
Rename Blackhawk to Cortex-X925.

Change-Id: I51e40a7bc6b8871c53c40d1f341853b1fd7fdf71
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-05-29 21:38:24 +02:00
Madhukar Pappireddy
dafa718bc9 Merge "fix(imx8m): 8mq: enable imx_hab_handler" into integration 2024-05-29 21:09:25 +02:00
Govindraj Raja
16aacab801 chore: rename Chaberton to Cortex-A725
Rename Chaberton to Cortex-A725.

Change-Id: I981b22d3b37f1aa6e25ff1f35aa156fff9c30076
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-05-29 13:48:56 -05:00
Jayanth Dodderi Chidanand
7d930c7e59 refactor(cm): move mpam registers into el2 context
* FEAT_MPAM related EL2 registers are placed explicitly outside
  the EL2 context in the cpu_context_t structure.

* With EL2 registers now coupled with dependent features, this
  patch moves them to the el2_context structure "el2_sysregs_t".

* Further, converting the assembly context-offset entries into a
  c structure. It relies on garbage collection of the linker
  removing unreferenced structures from memory, as well as aiding
  in readability and future maintenance.

Change-Id: Ib784bc8d2fbe35a8a47a569426d8663282ec06aa
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2024-05-29 17:01:51 +01:00
Madhukar Pappireddy
b690d244f2 Merge "fix(s32g274a): avoid overwriting const fields" into integration 2024-05-29 16:16:22 +02:00
Julius Werner
31309da016 Merge "feat(mt8188): update SVP region ID and permission" into integration 2024-05-29 07:37:36 +02:00
Madhukar Pappireddy
278b0885eb Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration
* changes:
  feat(imx8mp): optionally take params from BL2
  feat(imx8mn): optionally take params from BL2
  feat(imx8mm): optionally take params from BL2
  feat(imx93): optionally take params from BL2
  feat(imx): add helper to take params from BL2
2024-05-28 16:27:53 +02:00
Soby Mathew
261edb6a0f Merge changes I710d1780,Ia9a59bde into integration
* changes:
  feat(gpt): configure memory size protected by bitlock
  feat(gpt): add support for large GPT mappings
2024-05-28 12:26:37 +02:00
Olivier Deprez
3e8f9fd872 Merge "feat(mt8188): update the memory usage for SCP core0 and core1" into integration 2024-05-27 10:10:44 +02:00
Haohao Sun
fc77c69a17 feat(mt8188): update SVP region ID and permission
- Update SVP EMI-MPU region ID from 4 to 5 for resolving
  the issue of duplicate region ID used by the DSP.
- For SVP EMI-MPU region, modify domain 1 and domain 6 APC from
  FORBIDDEN to SEC_RW.
- Correct the calculation for the end address of SVP DRAM region.
- Add region 0 and region 1 for BL31 and BL32 memory protection.
- Add clear region protection API for SVP region.

Change-Id: Iaea348ad9be629e8a81cf579b148c6df66015b42
Signed-off-by: Haohao Sun <haohao.sun@mediatek.corp-partner.google.com>
2024-05-27 11:11:52 +08:00
Jason Chen
83112aa24f feat(mt8188): update the memory usage for SCP core0 and core1
- Reduce core0 memory usage from 41MB to 8MB.
- Increase core1 memory to 160MB to fulfill user-specific features.

Change-Id: I35547e2ac928945c244883d2333f921ce578bbd1
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
2024-05-27 11:11:43 +08:00
Yann Gautier
8dd2a64a12 feat(stm32mp15): remove OP-TEE shared mem
The flag STM32MP15_OPTEE_RSV_SHM was disabled and mark deprecated.
Remove the corresponding code.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I948af3e1de4b89815c967a63abe64f285c405ecc
2024-05-23 17:44:16 +02:00
Manish Pandey
f2735ebccf Merge "docs(changelog): changelog for v2.11 release" into integration 2024-05-23 13:51:22 +02:00
Manish V Badarkhe
669e2b159a docs(changelog): changelog for v2.11 release
Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.11.0

Change-Id: I34c7b342549781057da1b18116500f110bc3f5ad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <JuanPablo.Conde@arm.com>
2024-05-22 19:19:54 -05:00
Sergio Alves
dd5bf9c5e2 feat(tc): support full-HD resolution for the FVP model
Enable full-HD resolution (1920x1080p60) for the FVP model, and add
checking for the passed resolution parameter.

Change-Id: I5e37ae79b5ceac088a18d5acf00ff4a557bb56aa
Signed-off-by: Sergio Alves <sergio.dasilvalves@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
2024-05-22 17:20:57 +01:00
Manish Pandey
6370f2cbbe Merge changes from topic "hm/rt-instr" into integration
* changes:
  docs(juno): update PSCI instrumentation data
  docs(n1sdp): update N1SDP PSCI instrumentation data
2024-05-22 17:00:03 +02:00
Jackson Cooper-Driver
5ab7a2f2ea feat(tc): add MHUv3 addresses between RSS and AP
TC3 is upgraded to MHUv3. This patch adds the address of the MHU
channel to be used by TF-A for communications with the RSS.

Change-Id: I1bf5d72dc92bcd9d0509ba806095b24293875e85
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
2024-05-22 15:58:57 +01:00
Jackson Cooper-Driver
04085d6eb4 feat(tc): specify MHU version based on platform
Platforms older than TC2 contain MHUv2 well as newer platforms contain
MHUv3. Set the Makefile variable accordingly.

Change-Id: I00b83a34908cdbf7d1d9ac39728e3fa6ef449d2c
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
2024-05-22 15:58:57 +01:00
Boyan Karatotev
f2596ff1a8 feat(tc): bind SCMI over MHUv3 for TC3
TC2 and TC3 have different the scmi shared memory regions and MHU
parameters, this patch appends the properties in scmi node for TC2 and
TC3 respectively.

Change-Id: Ifd001f780b575987877b4be36eb755a9dbe57e60
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
2024-05-22 15:58:57 +01:00
Boyan Karatotev
6c069e7168 feat(tc): add MHUv3 DT binding for TC3
MHUv3's device tree is different from MHUv2's. Add support MHUv3 DT
binding for TC3 while keeping TC2 as-is.

Change-Id: Ib2f55d3a64a4cfe2ea9e62fe39d27ed54a2ca007
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
2024-05-22 15:58:57 +01:00
Leo Yan
4f65c0beaa feat(tc): add MHUv3 doorbell support on TC3
Enables the doorbell channels in MHUv3 for TC3.

Change-Id: Ib4f47df3e54f9182939ea6c1d8bc1a66a3c03094
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
2024-05-22 15:58:49 +01:00
Leo Yan
d2b1eb80af refactor(tc): change tc_scmi_plat_info to single structure
Currently, as the Total Compute system uses a single channel for MHU,
it's useless to define the structure 'tc_scmi_plat_info' as an array.
Change it as a single structure.

Change-Id: Iaa7c853327e7f5e67ccc14d12c5f0ef68d75dfd7
Signed-off-by: Leo Yan <leo.yan@arm.com>
2024-05-22 15:57:58 +01:00
Manish V Badarkhe
217bbf2a45 Merge "docs: move DPE option to experimental section" into integration 2024-05-22 16:48:56 +02:00
Manish V Badarkhe
b5ead359f3 docs: move DPE option to experimental section
Since DPE support is experimental, move the build option for
the DPE to the experimental section.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2e18947d37c52a0151b5ac656098dbae51254956
2024-05-22 14:13:50 +01:00
AlexeiFedorov
d766084fc4 feat(gpt): configure memory size protected by bitlock
This patch adds support in GPT library for configuration
of the memory block size protected by one bit of 'bitlock'
structure. Build option 'RME_GPT_BITLOCK_BLOCK' defines the
number of 512MB blocks covered by each bit. This numeric
parameter must be a power of 2 and can take the values from
0 to 512. Setting this value to 0 chooses a single spinlock
for all GPT L1 table entries. The default value is set to 1
which corresponds to 512MB per bit.

Change-Id: I710d178072894a3ef40daebea701f74d19e8a3d7
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
2024-05-22 11:41:00 +01:00
Harrison Mutai
932d6cdb25 docs(juno): update PSCI instrumentation data
Add the latest instrumentation data as of v2.11-rc0, remove data for
v2.9.

Change-Id: I8c055278d732220a9be88978ed63d27e453b7f2f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-05-21 13:25:16 +00:00
Harrison Mutai
e9c335fbda docs(n1sdp): update N1SDP PSCI instrumentation data
Add data for v2.11 release and remove data from v2.9.

Change-Id: Ic960cece6f27993cefebf483c768967bd6f2cad1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-05-21 13:25:16 +00:00
Manish V Badarkhe
842fe7113c Merge "docs(maintainers): update the maintainer list for LTS" into integration 2024-05-17 16:14:27 +02:00
Bipin Ravi
3ab6ae4ef4 docs(maintainers): update the maintainer list for LTS
This patch updates the maintainer list for LTS.

Change-Id: I7942288cd79dd163bebd3397bf908bf29906d59e
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2024-05-16 16:17:35 -05:00
Olivier Deprez
5b986f0188 Merge "build: allow shell commands in CC and friends" into integration 2024-05-16 18:10:08 +02:00
Manish V Badarkhe
91ec786ebd Merge changes from topic "mp/code_owners_doc" into integration
* changes:
  docs(maintainers): add code owners for runtime services module
  docs(maintainers): add missing header files
  docs(maintainers): add code owners for context management module
  docs(maintainers): add code owners for runtime exceptions module
  docs(maintainers): add missing files related to SPMD
  docs(maintainers): update missing files related to EL3 SPMC
2024-05-15 21:53:25 +02:00
Madhukar Pappireddy
b131a12377 docs(maintainers): add code owners for runtime services module
This patch adds code owners responsible for maintaining source files
related to runtime services functionality in TF-A.

Change-Id: I24fbbfd017f90a4fae2ffbb94c8eb81d0d837f8e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:56:04 -05:00
Madhukar Pappireddy
017566560e docs(maintainers): add missing header files
Few header files are added to the lists tracking code owners of
various modules in TF-A project.

Also remove drivers/nuvoton directory, which does not exist, from the list
of files maintained by the corresponding owners.

Change-Id: Iad7ce5b1430965237004c9e76e972a3469d20c9d
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:56:04 -05:00
Madhukar Pappireddy
5ecb6bb0bf docs(maintainers): add code owners for context management module
This patch adds code owners responsible for maintaining context
management source files in TF-A.

Change-Id: Idc679a907b8380e81d5fbb129fcb74cea5983c0e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:56:04 -05:00
Madhukar Pappireddy
4d16bc70bf docs(maintainers): add code owners for runtime exceptions module
This patch adds code owners responsible for maintaining runtime
exceptions and interrupt management modules in TF-A.

Change-Id: Idb131a2af143097e4d05a285e08ef12cd5d3db2a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:56:04 -05:00
Madhukar Pappireddy
a45f75a6a7 docs(maintainers): add missing files related to SPMD
Few header files are added to the list maintained by SPMD code owners.
Also, added myself as one of the code owners for SPMD module in TF-A.

Change-Id: Ic017cb98013d349702c35837463586d4aae65543
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:56:04 -05:00
Madhukar Pappireddy
46fc25019f docs(maintainers): update missing files related to EL3 SPMC
Few header files are added to the list maintained by EL3 SPMC
code owner.

Also added missing copyright license footer message.

Change-Id: I72afe4c4e1280ef64610a5efe6d1b0e2c9727bb0
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:55:21 -05:00